Path: ...!weretis.net!feeder6.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: "Mini" tags to reduce the number of op codes
Date: Sun, 7 Apr 2024 21:22:50 +0000
Organization: Rocksolid Light
Message-ID: <d71c59a1e0342d0d01f8ce7c0f449f9b@www.novabbs.org>
References: <uuk100$inj$1@dont-email.me> <6mqu0j1jf5uabmm6r2cb2tqn6ng90mruvd@4ax.com> <15d1f26c4545f1dbae450b28e96e79bd@www.novabbs.org> <lf441jt9i2lv7olvnm9t7bml2ib19eh552@4ax.com> <uuv1ir$30htt$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="434009"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="PGd4t4cXnWwgUWG9VtTiCsm47oOWbHLcTr4rYoM0Edo";
User-Agent: Rocksolid Light
X-Rslight-Site: $2y$10$S6/F.OSUdAdpQKCF/ypUae8WizQ4TQ74y.lEDFYl5m9SjZbk9or3G
X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8
X-Spam-Checker-Version: SpamAssassin 4.0.0
Bytes: 3171
Lines: 46

Thomas Koenig wrote:

> John Savard <quadibloc@servername.invalid> schrieb:

>> Thus, instead of having mode bits, one _could_ do the following:
>>
>> Usually, have 28 bit instructions that are shorter because there's
>> only one opcode for each floating and integer operation. The first
>> four bits in a block give the lengths of data to be used.
>>
>> But have one value for the first four bits in a block that indicates
>> 36-bit instructions instead, which do include type information, so
>> that very occasional instructions for rarely-used types can be mixed
>> in which don't fill a whole block.
>>
>> While that's a theoretical possibility, I don't view it as being
>> worthwhile in practice.

> I played around a bit with another scheme:  Encoding things into
> 128-bit blocks, with either 21-bit or 42-bit or longer instructions
> (or a block header with six bits, and 20 or 40 bits for each
> instruction).

Not having seen said encoding scheme:: I suspect you used the Rd=Rs1
destructive operand model for the 21-bit encodings. Yes :: no ??
Otherwise one has 3×5-bit registers = 15-bits leaving only 6-bits
for 64 OpCodes. Now if you have floats and doubles and signed and
unsigned, you get 16 of each and we have not looked at memory 
references or branching.

> Did that look promising?  Not really; the 21 bits offered a lot
> of useful opcode space for two-register operations and even for
> a few of the often-used three-register, but 42 bits was really
> a bit too long, so the advantage wasn't great.  And embedding
> 32-bit or 64-bit instructions in the code stream does not really
> fit the 21-bit raster well, so compared to an ISA which can do so
> (like My 66000) it came out at a disadvantage.  Might be possible
> to beat RISC-V, though.

But beating RISC-V is easy, try getting you instruction count down 
to VAX counts without losing the ability to pipeline and parallel
instruction execution.

At handwaving accuracy::
VAX      has 1.0 instructions
My 66000 has 1.1 instructions
RISC-V   has 1.5 instructions