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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Misc: BGBCC targeting RV64G, initial results...
Date: Sat, 5 Oct 2024 23:10:32 +0000
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On Thu, 3 Oct 2024 8:20:46 +0000, BGB wrote:

> On 10/1/2024 5:00 AM, Robert Finch wrote:
>> On 2024-09-29 10:19 p.m., BGB wrote:
>>>>>> The ADD is not necessary if min == 0
>>>>>>
>>>>>> The JTT instruction compared Rt with 0 on the low side and max
>>>>>> on the high side. If Ri is out of bounds, default is selected.
>>>>>>
>>>>>> The table displacements come in {B,H,W,D} selected in the JTT
>>>>>> (jump through table) instruction. Rt indexes the table, its
>>>>>> signed value is <<2 and added to address which happens to be
>>>>>> address of JTT instruction + #(max+1)<<entry. {{The table is
>>>>>> fetched through the ICache with execute permission}}
>>>>>>
>>>>>> Thus, the table is PIC; and generally 1/4 the size of typical
>>>>>> switch tables.

>> How well does JTT work with large tables? What if there are several
>> hundred table entries?

Tables can have 2^16-1 (65534) case entries.

>> For Q+ indirect jump the values loaded from the table replace the low
>> order bits of the PC instead of being a displacement. Only {W,T,O} are
>> supported. (W=wyde,T=tetra,O=octa). Should add an option for
>> displacements. Borrowed the memory indirect jump from the 68k.

My 66000 Loads the table entry directly into IP in 1 cycle less
than LD latency.

>