Path: ...!weretis.net!feeder6.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Stealing a Great Idea from the 6600
Date: Wed, 17 Apr 2024 23:32:20 +0000
Organization: Rocksolid Light
Message-ID: <e2097beb24bf27eed0a92f14596bd59e@www.novabbs.org>
References: <lge02j554ucc6h81n5q2ej0ue2icnnp7i5@4ax.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="1503866"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="PGd4t4cXnWwgUWG9VtTiCsm47oOWbHLcTr4rYoM0Edo";
User-Agent: Rocksolid Light
X-Rslight-Site: $2y$10$oBXoA.3STq5/9re52fHsd.8.F4VsNJrofLfhDUcUv9H9eu1BwfsH6
X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8
X-Spam-Checker-Version: SpamAssassin 4.0.0
Bytes: 1965
Lines: 17

While I much admire CDC 6600 PPs and how much work those puppies did
allowing the big number crunchers to <well> crunch numbers::

With modern technology allowing 32-128 CPUs on a single die--there is
no reason to limit the width of a PP to 12-bits (1965:: yes there was
ample reason:: 2024 no reason whatsoever.) There is little reason to
even do 32-bit PPs when it cost so little more to get a 64-bit core.

In 2005-6 I was looking into a Verilog full x86-64 core {less FP} so
that those smaller CPUs could run ISRs and kernel codes to offload the
big CPUs from I/O duties. Done in Verilog meant anyone could compile it
onto another die so the I/O CPUs were out on the PCIe tree nanoseconds
away from the peripherals rather than microseconds away. Close enough
to perform the DMA activities on behalf of the devices; and consuming
interrupts so the bigger cores did not see any of them (except timer).

As Scott stated:: there does not seem to be any reason to need FP on a
core only doing I/O and kernel queueing services.