Deutsch English Français Italiano |
<e369e386b23628e5388e95b5a92af62d@www.novabbs.org> View for Bookmarking (what is this?) Look up another Usenet article |
Path: ...!news.misty.com!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: My 66000 and High word facility Date: Wed, 14 Aug 2024 22:19:32 +0000 Organization: Rocksolid Light Message-ID: <e369e386b23628e5388e95b5a92af62d@www.novabbs.org> References: <v98asi$rulo$1@dont-email.me> <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org> <v991kh$vu8g$1@dont-email.me> <2024Aug11.163333@mips.complang.tuwien.ac.at> <v9b57p$2rkrq$1@dont-email.me> <v9brm4$33kmd$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="2596238"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Rslight-Site: $2y$10$boPsUp9k7q0HBUs4Nqx3qeOBlaRGRvpAAZLeYsifrySv8WdsO61OG Bytes: 2426 Lines: 29 On Mon, 12 Aug 2024 2:23:00 +0000, Brett wrote: > BGB <cr88192@gmail.com> wrote: >> > > Another benefit of 64 registers is more inlining removing calls. > > A call can cause a significant amount of garbage code all around that > call, > as it splits your function and burns registers that would otherwise get > used. What I see around calls is MOV instructions grabbing arguments from the preserved registers and putting return values in to the proper preserved register. Inlining does get rid of these MOVs, but what else ?? > I can understand the reluctance to go to 6 bit register specifiers, it > burns up your opcode space and makes encoding everything more difficult. I am on record as stating the proper number of bits in an instruction- specifier is 34-bits. This is after designing Mc88K ISA, doing 3 generations of SPARC chips, 7 years of x86-64, and Samsung GPU (and my own efforts) Making the registers 6-bits would increase that count to 36-bits. 34-bits comes from having enough Entropy to encode what needs encoding and making careful data-driven choices on "what to put in and what to leave out" and finding a clever means to access vectorization and multi- precision calculations. Without both of those 36-would likely be the best option for the 32-register variants.