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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: "Mini" tags to reduce the number of op codes
Date: Thu, 11 Apr 2024 23:12:25 +0000
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Scott Lurndal wrote:

> "Paul A. Clayton" <paaronclayton@gmail.com> writes:
>>On 4/9/24 8:28 PM, MitchAlsup1 wrote:
>>> BGB-Alt wrote:
>>[snip]
>>>> Things like memcpy/memmove/memset/etc, are function calls in 
>>>> cases when not directly transformed into register load/store 
>>>> sequences.
>>> 
>>> My 66000 does not convert them into LD-ST sequences, MM is a 
>>> single instruction.
>>
>>I wonder if it would be useful to have an immediate count form of
>>memory move. Copying fixed-size structures would be able to use an
>>immediate. Aside from not having to load an immediate for such
>>cases, there might be microarchitectural benefits to using a
>>constant. Since fixed-sized copies would likely be limited to
>>smaller regions (with the possible exception of 8 MiB page copies)
>>and the overhead of loading a constant for large sizes would be
>>tiny, only providing a 16-bit immediate form might be reasonable.

> It seems to me that an offloaded DMA engine would be a far
> better way to do memmove (over some threshhold, perhaps a
> cache line) without trashing the caches.   Likewise memset.

Effectively, that is what HW does, even on the lower end machines,
the AGEN unit of the Cache access pipeline is repeatedly cycled,
and data is read and/or written. One can execute instructions not
needing memory references while LDM, STM, ENTER, EXIT, MM, and MS
are in progress.

Moving this sequencer farther out would still require it to consume
all L1 BW in any event (snooping) for memory consistency reasons.
{Note: cache accesses are performed line-wide not register width wide}

>>
>>>> Did end up with an intermediate "memcpy slide", which can handle 
>>>> medium size memcpy and memset style operations by branching into 
>>>> a slide.
>>> 
>>> MMs and MSs that do not cross page boundaries are ATOMIC. The 
>>> entire system
>>> sees only the before or only the after state and nothing in 
>>> between. 

> One might wonder how that atomicity is guaranteed in a
> SMP processor...

The entire chunk of data traverses the interconnect as a single
transaction. All interested 3rd parties (not originator nor
recipient) see either the memory state before the transfer or
after the transfer.