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Path: ...!news.misty.com!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Privilege Levels Below User Date: Wed, 23 Oct 2024 22:38:40 +0000 Organization: Rocksolid Light Message-ID: <e71e3eea5c1c0668451ae3109b4df55b@www.novabbs.org> References: <jai66jd4ih4ejmek0abnl4gvg5td4obsqg@4ax.com> <Z9I8O.13$2JEf.11@fx14.iad> <5h%8O.4327$wDZ.776@fx48.iad> <1316e4baa439de908666e38c39cd8c79@www.novabbs.org> <v433n6$34io0$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="3384917"; mail-complaints-to="usenet@i2pn2.org"; posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU"; User-Agent: Rocksolid Light X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71 X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$z4GiMtyC.KHE8n1dJhBan.LZShyTw/z1at.6xvOr8wJj0Qnt.V29i Bytes: 3081 Lines: 43 On Sun, 9 Jun 2024 2:23:35 +0000, Lawrence D'Oliveiro wrote: > On Sat, 8 Jun 2024 17:37:46 +0000, MitchAlsup1 wrote: > >> VAX was before common era Hypervisors, do you think VAX could have >> supported secure mode and hypervisor with their 4 levels ?? > > “Virtualization” was bandied about in the 1980s more as an idle, > theoretical concept rather than a practical one. > > The question was: was the instruction set defined so that code that was > designed to run in a privileged mode be run unprivileged, so that any > attempt to do privileged things would be trapped and emulated by the > real privileged code? And there was nothing it could do to discover > it wasn’t running in privileged mode? My 66000 ISA has this property, and it is used when hypervisors host hypervisors. On the other hand, there is only 1 privileged instruction which provides access to 4 separate control register spaces based on current Core-Stack level. > (Obviously performance was not the issue here, but correctness was.) > > For example, the VAX had a MOVPSL instruction that allowed read-only > access to the entire processor status register. Through this, > nonprivileged user-mode code could discover it was running in user mode, > which would blow the illusion. While illustrative, we have entered the realm where processor state is closer to a cache line in size than a register in size. And the processor (core) stack of software layers is closer to 4 cache lines in size. > The Motorola 680x0 family was I think properly virtualizable in this > sense. Or maybe the 68020 and 68030 were, but the 68040 was. I think the > Motorola engineers working on the ’040 asked if any customers were > interested in preserving the self-virtualization feature, and nobody > seemed to care. During 020 development and testing, there was a mode whereby each instruction executed raised every possible exception--this only found 99% of the virtualization problems.