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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: PCIe MSI-X interrupts
Date: Tue, 25 Jun 2024 00:50:46 +0000
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Scott,

Can you foresee any problem is I define the positions in the
physical address space as: <ECAM: My 66000-style>::

     <1:0>     must be 00 for word access
     <2:7>     standard MMI/O register
     <12:8>    extended MMI/O register
     <25:13>   growth space for registers or for functions
     <32:26>   PCIe Device, Function
     <40:32>   PCIe Bus
     <56:41>   PCIe Segment
     <63:57>   Chip

This effectively gives each B;D,F a 25-bit address space and
65K segments and up to 32 chips on a motherboard. Need more
space for functions? take as many bits as you like from the
left hand side. Need more register room? take bits from the
right hand side. Need more bits for Chip? Steal them from
PCIe segment.

I wanted to move B;D,F up a bit to separate it from the I/O
registers which will likely come out of a memory reference
immediate, and I wanted to position B from D,F across a MMU
translation level boundary.

I am expecting the code touching the MMI/O register to have
a virtual address pointer to B;D,F and use the 16-bit immediate
field of the LD or ST as the register specifier:

     ST    #command7,[Rdevice,#registername]

--------------------------------------------------------------
I am expecting to use the Chip field to route requests between
chips. It is plausible that physical device sends an interrupt
from its PCIe segment across one-or-more chips before arriving
at the interrupt service port in a particular chips last level
cache. Other than latency its all part of a large coherent DRAM
space.

Is that plausible ? desirable ? or are there reasons to keep
interrupt processing "more local" to the chip hosting the PCIe
root complexes ?? {in any event, that is all under SW control.|