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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Sun, 10 Nov 2024 01:26:22 +0000
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On Sat, 9 Nov 2024 23:18:14 +0000, Scott Lurndal wrote:

> "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:
>>On 11/8/2024 6:19 AM, Scott Lurndal wrote:
>>> Lawrence D'Oliveiro <ldo@nz.invalid> writes:
>
>>>
>>> A real world example from the linux kernel:
>>>
>>> static __always_inline s64
>>> __ll_sc_atomic64_dec_if_positive(atomic64_t *v)
>>> {
>>>          s64 result;
>>>          unsigned long tmp;
>>>
>>>          asm volatile("// atomic64_dec_if_positive\n"
>>>          "       prfm    pstl1strm, %2\n"
>>>          "1:     ldxr    %0, %2\n"
>>>          "       subs    %0, %0, #1\n"
>>>          "       b.lt    2f\n"
>>>          "       stlxr   %w1, %0, %2\n"
>>>          "       cbnz    %w1, 1b\n"
>>>          "       dmb     ish\n"
>>
>>"dmb ish" is interesting to me for some reason...
>
>   Data Memory Barrior - inner sharable coherency domain

It reads better without explanation ...