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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: My 66000 and High word facility
Date: Wed, 14 Aug 2024 22:26:27 +0000
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On Mon, 12 Aug 2024 6:29:36 +0000, Anton Ertl wrote:

> Brett <ggtgp@yahoo.com> writes:
>>Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
>>>
>>> Where is your 4% number coming from?
>>
>>The 4% number is poor memory and a guess.
>>Here is an antique paper on the issue:
>>
>>https://www.eecs.umich.edu/techreports/cse/00/CSE-TR-434-00.pdf
>
> Interesting.  I only skimmed the paper, but I read a lot about
> inlining and interprocedural register allocation.  SPARCs register
> windows and AMD29K's and IA-64's register stacks were intended to be
> useful for that, but somehow the other architectures did not suffer a
> big-enough disadvantage to make them adopt one of these concepts, and
> that's despite register windows/stacks working even for indirect calls
> (e.g., method calls in the general case), where interprocedural
> register allocation or inlining don't help.

The problem of register-windows is when "you miss the cache",
first you have to take the exception,
then you have to blindly push an IN or pull and OUT with no knowlege
of how many registers are in use (or several of them)
then you have to return from the exception.

So, you have two exception control transfers, and a blind copy of
fixed sized data, loss of a few TLB entries, and loss of a few
cache lines of data+instructions.

Whereas MIPS, 88k, Alpha, RISC-V always "hit in the cache" so to
speak.

There was an old paper that stated MIPS team had optimizing compiler up
and optimizing, while SPARC team bet on HW to compensate for their lack.
History has chose the non-SPARC path.