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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Stealing a Great Idea from the 6600
Date: Fri, 26 Apr 2024 13:25:03 +0000
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BGB wrote:

> On 4/25/2024 4:01 PM, George Neuner wrote:
>> On Tue, 23 Apr 2024 17:58:41 +0000, mitchalsup@aol.com (MitchAlsup1)
>> wrote:
>>

> Agreed in the sense that negative displacements exist.

> However, can note that positive displacements tend to be significantly 
> more common than negative ones. Whether or not it makes sense to have a 
> negative displacement, depending mostly on the probability of greater 
> than half of the missed displacements being negative.

>  From what I can tell, this seems to be:
>    ~ 10 bits, scaled.
>    ~ 13 bits, unscaled.


> So, say, an ISA like RISC-V might have had a slightly hit rate with 
> unsigned displacements than with signed displacements, but if one added 
> 1 or 2 bits, signed would have still been a clear winner (or, with 1 or 
> 2 fewer bits, unsigned a clear winner).

> I ended up going with signed displacements for XG2, but it was pretty 
> close to break-even in this case (when expanding from the 9-bit unsigned 
> displacements in Baseline).


> Granted, all signed or all-unsigned might be better from an ISA design 
> consistency POV.


> If one had 16-bit displacements, then unscaled displacements would make 
> sense; otherwise scaled displacements seem like a win (misaligned 
> displacements being much less common than aligned displacements).

What we need is ~16-bit displacements where 82½%-91¼% are positive.

How does one use a frame pointer without negative displacements ??

[FP+disp] accesses callee save registers
[FP-disp] accesses local stack variables and descriptors

[SP+disp] accesses argument and result values

> But, admittedly, main reason I went with unscaled for GBR-rel and PC-rel 
> Load/Store, was because using scaled displacements here would have 
> required more relocation types (nevermind if the hit rate for unscaled 
> 9-bit displacements is "pretty weak").

> Though, did end up later adding specialized Scaled GBR-Rel Load/Store 
> ops (to improve code density), so it might have been better in 
> retrospect had I instead just went the "keep it scaled and add more 
> reloc types to compensate" option.


> ....


>> YMMV.