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From: John Larkin <jjSNIPlarkin@highNONOlandtechnology.com>
Newsgroups: sci.electronics.design
Subject: Re: spread-spectrum model
Date: Sat, 20 Apr 2024 10:57:17 -0700
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On Sat, 20 Apr 2024 10:34:46 -0400, legg <legg@nospam.magma.ca> wrote:

>On Thu, 18 Apr 2024 12:14:04 -0700, John Larkin
><jjSNIPlarkin@highNONOlandtechnology.com> wrote:
>
>>On Thu, 18 Apr 2024 13:16:04 -0400, Joe Gwinn <joegwinn@comcast.net>
>>wrote:
>>
>>>On Thu, 18 Apr 2024 08:26:56 -0700, John Larkin
>>><jjSNIPlarkin@highNONOlandtechnology.com> wrote:
>>>
>>>>I'm designing a switching power supply module and could reduce EMI by
>>>>going spread-spectrum on the switching frequency. The simple one below
>>>>reduces things by 20 dB. Probe the SS node and FFT.
>>>>
>>>>The ss inside switching reg chips is no doubt more sophisticated. In
>>>>an FPGA, we could do some sort of pseudo-random thing.
>>>>
>>>>On a multi-channel power supply, there may be some small advantage to
>>>>have a separate spread per channel. That would be easy.
>>>
>>>I'd check for cross-correlation as well, so no ganging up in systems
>>>using multiple channels in some signal path.
>>
>>When my engineers get too fussy about stuff like that, I remind them
>>"it's just a power supply."
>
>Noise at the local level is best correlated, as it is more 
>predictable - you avoid low-frequency beat frequencies in the 
>local regulators - which can and will show up in a detector's 
>BW and in the regulators' outputs.

But...but... it's just a power supply!

Presumably uncorrelated spread-spectrum will make wideband noise at an
output, not a beat.

>
>A master clock, phase shifted for various local users, can be dithered
>for the system (box), which is the actual, final radiator.

Our box has a 50 MHz clock that is bussed to all the plugin modules,
and it can be locked to other boxes or to a 10 MHz reference, so we
can't usefully dither that. I guess each module could have its own
VCO, but that would mess up synchronizing modules, and complicate
things. Spread-spectrum sounds easier.

>
>Your engineers can get REAL fussy, if the system's non-compliant 
>way past the development's due date.

Eventually, some giant customer may want CE stickers, so we'll do the
easier things now, to improve our chances of passing an EMI test. A
bit of VHDL in the FPGAs would be easy.