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From: john larkin <jlarkin_highland_tech>
Newsgroups: sci.electronics.design,comp.arch.fpga,comp.sys.raspberry.pi
Subject: Re: configuring an Efinix T20
Date: Sat, 07 Sep 2024 08:58:02 -0700
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On Sat, 7 Sep 2024 15:19:59 +0100, John R Walliker
<jrwalliker@gmail.com> wrote:

>On 06/09/2024 23:50, john larkin wrote:
>> 
>> I'm planning to use a Raspberry Pi RP2040 processor chip to configure
>> and then talk to an Efinix T20-FG256 FPGA.
>> 
>> Has anyone done this, or at least configured a T20 from a
>> microprocessor?
>> 
>> The RP2040 only has 30 GPIO pins, and many are dedicated to other
>> stuff, so we want to share a lot of things on one giant SPI bus,
>> including the FPGA config and then an SPI port on the FPGA to read and
>> write registers.
>> 
>> It looks like four of the T20 config pins need pullups. I wonder why
>> their guidelines show four separate resistors. Why not one resistor?
>> Why have resistors at all?
>> 
>> SS_N needs a pulldown. Why not ground it?
>> 
>> https://www.dropbox.com/scl/fi/x0gvvwqg42vhryu6610ve/Efinix_Config_1.jpg?rlkey=udy24brtumvdzfd2sp4l6yhwf&raw=1
>> 
>> 
>> It's always a moment to celebrate when a "config done" LED lights up.
>> 
>> I could easily get this wrong, so it would be great if I posted some
>> schematics and notes and someone could eyeball them for me.
>
>If you need some more i/o pins, why not use the RP2350B?  They
>definitely exist - I have one in front of me:
>https://shop.pimoroni.com/products/pga2350?variant=42092629229651
>
>John

It only has two more package pins, as I recall. How many GPIOs?

It's new and a bit buggy and not widely available, so we'll stick with
the 2040. The only upsides are the higher clock rate and the faster
floats, which aren't critical in the product line that we are
developing now.

Why didn't they make it pin compatible, drop-in to the 2040? Why not
put in a mac/phy instead of the extra CPU cores?

Using one SPI bus for multiple loads will save pins. We should be able
to configure the FPGA and then read/write registers with a shared SPI
interface, and hit some other things too.

It might be tricky to share the interface to the WizNet ethernet chip,
and sharing the flash interface wires is something we don't want to
even think about.

Of course, once I have an FPGA, I'll have a zillion port pins
available.