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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: john larkin <JL@gct.com> Newsgroups: sci.electronics.design Subject: Re: faster DDS clock Date: Fri, 20 Sep 2024 07:49:01 -0700 Organization: A noiseless patient Spider Lines: 82 Message-ID: <ja2rejto6r37n02aoc8o5k91jigj6ec2r6@4ax.com> References: <vphmejhqgb8br7j2u5dq7dus2schvi2rpu@4ax.com> <vcfibb$7jcv$1@dont-email.me> <nb0nejl0b1h6p40b3lp9ebmn0ln78pdi10@4ax.com> <vcg5o9$e18t$1@dont-email.me> <3r7nejdbihkhugevrmvvkvos85roknqrv5@4ax.com> <vci8m4$o1le$3@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 20 Sep 2024 16:49:04 +0200 (CEST) Injection-Info: dont-email.me; posting-host="064518907d77aa3ca1b28d12fbd93e23"; logging-data="1218753"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/RYMiJFIYTL8/AOA5jV9h3" User-Agent: ForteAgent/8.00.32.1272 Cancel-Lock: sha1:uVb5hUwCtCniWIYjrhuWDaYvWP0= Bytes: 4238 On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk> wrote: >On 9/19/24 05:57, john larkin wrote: >> On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> john larkin <JL@gct.com> wrote: >>>> On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs >>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>> >>>>> john larkin <jl@650pot.com> wrote: >>>>>> Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock. >>>>>> >>>>>> Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>> >>>>>> >>>>> >>>>> The usual trouble is that you have to get the other edge from somewhere. An >>>>> xor gate and an RC is typical. >>>>> >>>>> Any asymmetry in the square wave turns into subharmonic jitter. >>>>> >>>>> A 2:1 PLL would probably get my vote. >>> >>>> >>>> I'm trying to make things cheaper and simpler. I need a clock that's >>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>> some relatively cheap dual DACs. >>> >>> Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>> it’s possible to use a TinyLogic inverter with VDD open.) >>> >>> Cheers >>> >>> Phil Hobbs >> >> An LVDS line receiver would make a pretty good comparator, after the >> filter. >> >> If I have enough balls (no pun intended) I can use an LVDS input of my >> FPGA. One could even servo that to exactly 50%. >> >> I don't know if this FPGA could internally clock on both edges. >> >> But I can get a TI DAC908 for under $5, so may just clock that fast, >> brute force at 100 MHz or so. That would make 20 MHz with a dinky >> filter. >> > >this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html That's cool. I need 4 DDSs so I'd use two of them, but it is still appealing. It looks like I'll have to use an Efinix T130 FPGA to get the RAM I need for waveform storage, so I'll have tons of logic and i/o's to go hard parallel to the DACs. I could use 10 or 9 or 8 bits if that is easier to route, and the current outputs dump right into the right kind of filter. I have a Spice model of a DDS clock generator. I wonder how awful a lowpass filter I can get away with. CLC? Or even RC? > >or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html > >if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html > > > > >