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From: Stefan Monnier <monnier@iro.umontreal.ca>
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Wed, 11 Sep 2024 10:33:16 -0400
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> I suspect at least theoretically conditions could exist where
> having more than one lock within a cache line would be beneficial.
> If lock B is always acquired after lock A, then sharing a cache
> line might (I think) improve performance. One would lose

I suspect in practice this almost never happens because if it did, it
would mean that the program would benefit from merging those two locks
into a single one.


        Stefan