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From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Fri, 10 May 2024 18:49:31 -0600
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On Thu, 2 May 2024 18:28:18 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

>John Savard wrote:
>
>> On Wed, 1 May 2024 23:17:06 -0000 (UTC), Lawrence D'Oliveiro
>> 
>
>> Plus, if you load a single precision float into a floating-point
>> register, you are loading on the left side, not the right side, so the
>
>In My 66000, floats are stored on the right side of the register
>{mostly because I do not have FP LD/STs.}

And _not only_ do I have FP loads and stores, but one of the things
they *do* is convert floats (if needed) to an internal form so that
the exponent is of the exact same form, in the same position, for all
the floats of that type.

The Compatible Floating Point loads and stores - those are the ones
for hexadecimal S/360 floats - just do left-aligned raw loads and
stores in the FP registers, since their exponents are all in the same
form.

But the regular ones, for IEEE 754 floats, convert everything to look
like the old 8087 temporary real format. Possibly with an extra
exponent bit to accomodate the new 128-bit format defined in IEEE 754.

Of course, you may rightfully say that is crazy - if I did a
computation saving everything in memory, or using short vectors (where
this conversion doesn't take place) then the computation strictly
observes the exponent range, but if I do one in registers, a
calculation could continue normally where an intermediate result ought
to have underflowed by a little bit.

But here I'm following Seymour Cray - sacrifice everything else for
speed. Although 'within reason'; _except for division_ I keep IEEE 754
exact results.

John Savard