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From: john larkin <jl@glen--canyon.com>
Newsgroups: sci.electronics.design
Subject: Re: Cap C-V test
Date: Sat, 03 May 2025 19:17:00 -0700
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On Sun, 4 May 2025 02:11:47 +0200, Lasse Langwadt <llc@fonz.dk> wrote:

>On 5/1/25 22:09, john larkin wrote:
>> 
>> https://www.dropbox.com/scl/fi/a7425c69k3w8wx8tqjpq5/X110_CV_Test.jpg?rlkey=pc3c0b12ncswv6ajrn148stdk&raw=1
>> 
>> 
>> The DUT is a Venkel 2.2 uF 100v 1812-size ceramic cap. I need to run
>> it at 48 volts. 0.8 uF is probably OK. I have room on my board so I
>> guess I'll add another cap in parallel.
>
>or in series, I believe there are some automotive standards that call 
>for that on high current lines because ceramics tend to fail short with 
>mechanical stress
>

Two of those caps in series would make about half the capacitance of
two in parallel, but ESR and ESL would suffer by 4:1.

We don't see many ceramic cap failures. Our worst parts are "sealed"
relays that actually aren't. Some switches, too.

We don't use surface-mount film caps. They are awful.