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From: jgd@cix.co.uk (John Dallman)
Newsgroups: comp.arch
Subject: Re: Oops (Concertina II Going Around in Circles)
Date: Fri, 10 May 2024 00:19 +0100 (BST)
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In article <ofeq3j9ni63e7tmccf2qbkb9t0naui44ei@4ax.com>,
quadibloc@servername.invalid (John Savard) wrote:

> On Thu, 9 May 2024 20:28 +0100 (BST), jgd@cix.co.uk (John Dallman)
> wrote:
> >I think you've just added another couple of orders of magnitude to 
> >the odds against that happening. 
> 
> What, you don't think that an ISA that is capable of handlling an
> instruction set two orders of magnitude larger than ordinary
> instruction sets wouildn't have a highly sought-after feature, at
> least for some niches?

Not that justified the costs of implementing such a huge instruction set.
All the transistors that go into that are not going into performance
(caches, functional units, and OoO pool size) and are pushing up the size
of the minimal implementation. 

Also, teaching development tools about vast instruction sets is likely to
demonstrate the RISC lesson again: compilers only use the simple parts. 

John