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Path: ...!3.eu.feeder.erje.net!feeder.erje.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: jgd@cix.co.uk (John Dallman) Newsgroups: comp.arch Subject: Re: Computer architects leaving Intel... Date: Wed, 28 Aug 2024 19:49 +0100 (BST) Organization: A noiseless patient Spider Lines: 23 Message-ID: <memo.20240828194931.19028s@jgd.cix.co.uk> References: <w%JzO.33560$95o8.18523@fx09.iad> Reply-To: jgd@cix.co.uk Injection-Date: Wed, 28 Aug 2024 20:49:31 +0200 (CEST) Injection-Info: dont-email.me; posting-host="49d57e041fd6c3fe611ce201ea4c043c"; logging-data="3770747"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Id4Nlyv/CfkgNhWZiE2CUy5OivnVUSsE=" Cancel-Lock: sha1:dKAabKeekUVdKOBdTApTdmysLKY= X-Clacks-Overhead-header: GNU Terry Pratchett Bytes: 1962 In article <w%JzO.33560$95o8.18523@fx09.iad>, scott@slp53.sl.home (Scott Lurndal) wrote: > > Intel were all over RISC-V in 4Q2022 and 1Q2023, looking for > > something to compete with ARM after having accepted you can't > > get power:performance to match ARM out of x86-64. Then it all > > went quiet, and Intel didn't manufacture the SiFive SoC > > ("Horse Creek") that was supposed to blaze the trail for > > RISC-V as a consumer and/or enterprise architecture. > > The problem with this is that RISC-V isn't currently comparable, > feature-wise, with ARMv8.0. To compete with Neoverse-N2 cores, > they'll need to support a similar feature set - most of which > doesn't exist in the RISC-V design space yet. Open-source design of the ISA has delivered an architecture suitable for teaching, its original purpose, but has failed to promptly deliver the dull-but-necessary features for large-scale systems? I'm shocked! Surely SiFive should have done this work, if they'd known what they were doing in competing with ARM? John