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NNTP-Posting-Date: Sun, 01 Dec 2024 22:58:56 +0000
From: Joe Gwinn <joegwinn@comcast.net>
Newsgroups: sci.electronics.design
Subject: Re: DDS follies
Date: Sun, 01 Dec 2024 17:58:55 -0500
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On Sat, 30 Nov 2024 19:43:08 -0800, john larkin <JL@gct.com> wrote:

>We have an old product, a 4-channel arb, that specifically simulates
>pickups from complex rotating machines, namely jet engines.
>
>https://highlandtechnology.com/Product/V375
>
>It has four DDS clock synthesizers; I used AD9830s and fancy LC
>filters and comparators for the clocks. They have 32-bit frequency set
>registers and I'm clocking at 40 MHz, max out 15 MHz.
>
>The design is 22 years old and, amazingly, 2024 has been its best
>selling year ever. But all sorts of stuff is going EOL so I have to
>redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
>all the waveform memories on-chip.
>
>I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
>jocks have suggestions.
>
>We do need the *exact* same settability as the ADI part, and it's
>critical that, if we set several frequencies at some multiple of the
>lowest one, the frequencies are exact and the phase relationships
>never change; gears don't change their teeth or slip.
>
>Jitter isn't too big a deal; we are simulating machines.
>
>I was thinking that I might do some 32-bit phase accumulators in my
>FPGA, from the highest clock frequency it can stand, and only pull out
>a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
>filters and schmitt gate comparators, then divide down. The max final
>frequency could be maybe 20 or 25 MHz, somewhat higher than the old
>system could do.
>
>Any thoughts or dirty tricks? I'll brainstorm this with my
>signals-and-systems jocks, but want to think about it first so I don't
>look too silly.

In the radar world, we use two-stage DDSs implemented in a big FPGA.
The first stage generates the phase increment, the second generates a
phase slope by cyclic accumulation of phase increments, rolling over
once per full cycle.  The resulting phase sawtooth is fed to either a
lookup table or a CORDIC module of some kind.  There are thousands of
variations.  The reason for two stages is to create perhaps non-linear
frequency chirps.

Analog Devices used to have a guide to DDS principles, from which to
get ideas.  Then implement only what is needed in a FPGA.  Unless you
are going for very precise sinewaves, the lookup table need not be all
that large.

Joe Gwinn