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From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Stealing a Great Idea from the 6600
Date: Fri, 19 Apr 2024 01:38:45 -0600
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On Thu, 18 Apr 2024 23:42:15 -0600, John Savard
<quadibloc@servername.invalid> wrote:


>Each core can just switch between compute duty with N threads, and I/O
>service duty with 4*N threads - or anywhere in between.

So I hope it is clear now I'm talking about SMT threads, not cores.
Threads are orthogonal to cores.

But I did make one oversimplification that could be confusing.

The full instruction set assumes banks of 32 registers, one each for
integer and floats, the reduced instruction set assumes banks of 8
registers, one each for integer and floats.

So one thread of the full ISA can be replaced by four threads of the
reduced ISA, both use the same number of registes.

That's all right for an in-order design. But in real life, computers
are out-of-order. So the *rename* registers would have to be split up.

Since the reduced ISA threads are four times greater in number, their
instructions have four times longer to finish executing before their
thread gets a chance to execute again. So presumably reduced ISA
threads will need less agressive OoO, and 1/4 the rename registers
might be adequate, but there's obviously no guarantee that this would
indeed be an ideal fit.

John Savard