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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Tonight's tradeoff
Date: Thu, 7 Mar 2024 16:02:45 -0500
Organization: A noiseless patient Spider
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On 2024-03-07 2:51 p.m., MitchAlsup1 wrote:
> Robert Finch wrote:
> 
>> On 2024-03-07 1:39 a.m., BGB wrote:
>>>
>>>
>> Bigfoot uses a whole byte for access rights, with separate 
>> read-write-execute for user and supervisor, and write protect for 
>> hypervisor and machine modes. He also uses 4 bits for the 
>> cache-ability which match the cache-ability bits on the bus.
> 
> Can you think of an example where a user Read-Only page would not be
> writeable from super ?? Or a device on PCIe ??
> Can you think of an example where a user Execute-Only page would not
> be readable from super ?? Or a device on PCIe ??

I cannot think of examples. But I had thought the hypervisor / machine 
might want to treat supervisor mode like an alternate user mode. The 
bits can always just be set = 7.


> Can you think of an example where a user page marked RWE = 000 would
> not be readable and writeable from super ? Or a device on PCIe ??
> 
A page marked RWE=000 is an unusable page. Perhaps to signal bad memory. 
Or perhaps as a hidden data page full of comments or remarks. If its not 
readable-writeable or executable what is it? Nothing should be able to 
access it, except maybe the machine/debug operating mode.


> Can you think of an example where 2-bits denoting {L1, L2, LLC, DRAM}
> does not describe the cache placement of a line adequately ??
> 
The cache-ability bits were not directly describing cache placement. 
They were like the cache-ability bits in the bus. They specified 
cache-policy. Bufferable / non-bufferable. Write-through, write-back, 
allocate, etc. But now that I reviewed it I forgot I had removed these 
bits from the PTE / TLBE.

I do not like situations where all possible codes are used. So, I would 
probably use three bits. Could a cache line be located in a Register for 
instance?

I cannot envision every usage, although a lot is known today, I thought 
it would be better to err on the side of providing too many bits rather 
than not enough. Not enough is hard to add later. There are loads of 
bits available in the 128-bit PTE, 96 bits would be enough. But it is 
not a nice power of two.

> 
>> I am using the value of zero for the ASID to represent the machine 
>> mode’s ASID. A lot of hardware is initialized to zero at reset, so 
>> it’s automatically the machine mode’s. Other than zero the ASID could 
>> be anything assigned by the OS.
> 
> I do not rely on control registers being set to zero, instead part of
> HW context switching end up reading these out of ROM and into those
> registers--so they can have any reasonable bit pattern SW desires.
> {{This is sort of like how Alpha comes out of reset and streams a ROM
> through the scan path to initialize the internals.}}
> 
> I am also assuming that ASID = 0 is the highest level of privilege;
> but this is purely a SW choice.

Assuming a zero at reset was more of a default ‘if I forget’ approach. I 
have machine state being initialized from ROM too.