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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Capabilities, Anybody?
Date: Wed, 13 Mar 2024 14:17:20 -0400
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On 2024-03-13 11:53 a.m., MitchAlsup1 wrote:
> Robert Finch wrote:
> 
>> Can capabilities be applied to address ranges?
> 
> That is a major thing that they provide.
> 
>> Segmentation similar to the PowerPC 32-bit segmentation is being used 
>> in the current project. Where the upper address bits select a segment 
>> register which provides more address bits. I would like to use the 
>> same descriptors for capabilities and the address range segmentation.
> 
> How would you handle 2 billion Capabilities in a single application ??
> 
> Each of which have a range of 2 GB each ??? and each containing at
> least 1 M Capabilities ????

I should have been a bit more clear maybe, it has taken time to gel in 
my head.

PowerPC-32 has only 16 segment registers. I think these could be 
extended to capabilities registers in the same manner as proposed for 
the FS, GS registers in x64. I wonder if there is any value in doing so 
though, since the address is a constant. I think it should already be 
known if it would exceed a bounds. The segment registers simply tack on 
24-bits to the left side of the remaining address bits to generate a 
52-bit virtual address. I think all a capability would do is provide a 
slightly different means to calculate the address.

I have a couple of cores I can experiment with adding capabilities. For 
my current project there are 32 segment registers.

******

I am wondering if the ‘R’ term in the CHERI concentrate expansion calc 
can be less than zero or if it is a modulo value. It is shown as 
B[13:11] – 1. I am assuming it can go negative and is not modulo.

How “open” is CHERI ? Can CHERI based code be posted?