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From: Terje Mathisen <terje.mathisen@tmsw.no>
Newsgroups: comp.arch
Subject: Re: Cray style vectors
Date: Fri, 15 Mar 2024 10:33:21 +0100
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Anton Ertl wrote:
> Terje Mathisen <terje.mathisen@tmsw.no> writes:
>> Tim Rentsch wrote:
>>> Terje Mathisen <terje.mathisen@tmsw.no> writes:
>>>
>>>> If I really had to write a 64x64->128 MUL, with no widening MUL or
>>>> MULH which returns the high half, then I would punt and do it using
>>>> 32-bit parts (all variables are u64):  [...]
>>>
>>> I wrote some code along the same lines.  A difference is you
>>> are considering unsigned multiplication, and I am considering
>>> signed multiplication.
>>>
>> Signed mul is just a special case of unsigned mul, right?
>>
>> I.e. in case of a signed widening mul, you'd first extract the signs,
>> convert the inputs to unsigned, then do the unsigned widening mul,
>> before finally resotirng the sign as the XOR of the input signs?
> 
> In Gforth we use:
> 
> DCell mmul (Cell a, Cell b)		/* signed multiply, mixed precision */
> {
>    DCell res;
> 
>    res = UD2D(ummul (a, b));
>    if (a < 0)
>      res.hi -= b;
>    if (b < 0)
>      res.hi -= a;
>    return res;
> }
> 
> I have this technique from Andrew Haley.  It relies on twos-complement
> representation.

Nice!

Subtracting the results of having used the sign bit as part of the 
multiplication.

Here you can probably schedule the fixup to happen in parallel with the 
actual multiplication:

;; inputs in r9 & r10, result in rdx:rax, rbx & rcx as scratch

   mov rax,r9	;; All these can start in the first cycle
   mul r10
   mov rbx,r9	;; The MOV can be handled by the renamer
   sar r9,63
   mov rcx,r10	;; Ditto
   sar r10,63

   and rbx,r9	;; Second set of ops
   and rcx,r10

   add rbx,rcx	;; Third cycle

   sub rdx,rbx	;; Do a single adjustment as soon as the MUL finishes

Terje

-- 
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"