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From: Klaus Vestergaard Kragelund <klauskvik@hotmail.com>
Newsgroups: sci.electronics.design
Subject: Re: +48 precharge
Date: Fri, 29 Mar 2024 11:54:02 +0100
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On 24-03-2024 23:16, John Larkin wrote:
> On Sun, 24 Mar 2024 16:10:25 -0400, Joe Gwinn <joegwinn@comcast.net>
> wrote:
> 
>> On Sun, 24 Mar 2024 12:14:57 -0700, John Larkin
>> <jjlarkin@highlandtechnology.com> wrote:
>>
>>>
>>> We have a board that tends to blow up.
>>>
>>> It has a couple of isolated dc/dc converters, gate driver chips and
>>> big mosfet full-bridges driving transformers. The gate drivers get
>>> their inputs from an FPGA.
>>>
>>> The probelm is that the +48 volts to the h-bridges comes up at power
>>> turn-on, but the FPGA is configured some minutes later, after Linux
>>> boots up. And I don't entirely trust the FPGA outputs meanwhile.
>>> Possibly never.
>>>
>>> After designing many complex fixes, a simple fix is to precharge the
>>> module's +48 rail gently, and slam it on hard after everything is
>>> verified stable.
>>>
>>>
>>> <https://www.dropbox.com/scl/fi/i7mgvnad9h1itxf8p0t76/P941_942_Precharge_1.jpg?rlkey=tv3rh3kzlw40th20oes6hlhr2&raw=1>
>>>
>>>
>>> The one-shot gets its I'M OK trigger from the FPGA, which can only
>>> happen if the FPGA is working, I hope.
>>
>> Can you require significant net charge transfer on a short period of
>> time from the FPGA before the one-shot will trigger?
>>
>> Joe Gwinn
> 
> The retriggerable one-shot is 1 microsecond, and the FPGA (once it's
> alive and well) will clock it at 2 MHz. No clock, no hard +48.
> 
> We'll have seconds available to charge the filter caps, before we make
> the I'M_OK signal to enable stuff. It a Linux system!
> 
> 
> 
> 
> 

The FPGA will have a defined state during startup, and your gatedrivers 
have UVLO, so during boot the FPGAs are defined as high-z, and you use a 
pull-down resistor to pull the outputs low during boot. Normally you 
would use a delay for the VDD for the gatedrivers, so both ramping VCC 
and controlled VDD start makes sure there are no conflict.

I am currently working on a 3MW converter. We are controlling it 
directly from a FPGA, like described above.

When I worked at Vestas doing 6MW wind turbine, we did it the same way.

Cheers

Klaus