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Path: ...!news.nobody.at!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Lawrence D'Oliveiro <ldo@nz.invalid> Newsgroups: comp.arch Subject: Re: Short Vectors Versus Long Vectors Date: Wed, 24 Apr 2024 02:47:59 -0000 (UTC) Organization: A noiseless patient Spider Lines: 20 Message-ID: <v09rsv$236so$1@dont-email.me> References: <v06vdb$17r2v$1@dont-email.me> <5451dcac941e1f569397a5cc7818f68f@www.novabbs.org> <hqmg2j1vbkf6suddfnsh3h3uhtkqqio4uk@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Apr 2024 04:47:59 +0200 (CEST) Injection-Info: dont-email.me; posting-host="13b1d2d556e95ece6587b97b13572e96"; logging-data="2202520"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19HhVjU/K406s+MwURuflWi" User-Agent: Pan/0.155 (Kherson; fc5a80b8) Cancel-Lock: sha1:8PTohrcAaw9010+pnyE/MnMGmyM= Bytes: 1914 On Tue, 23 Apr 2024 19:25:22 -0600, John Savard wrote: > After all, the reason the Cray I succeeded where the STAR-100 failed was > that it had those big vector registers ... Looking at an old Cray-1 manual, it mentions, among other things, sixty four 64-bit intermediate scalar “T” registers, and eight 64-element vector “V” registers of 64 bits per element. That’s a lot of registers. RISC-V has nothing like this, as far as I can tell. Right at the top of the spec I linked earlier, it says: The vector extension adds 32 architectural vector registers, v0-v31 to the base scalar RISC-V ISA. Each vector register has a fixed VLEN bits of state. So, no “big vector registers” that I can see? It says that VLEN must be a power of two no bigger than 2**16, which does sound like a lot, but then the example they give only has VLEN = 128.