Deutsch   English   Français   Italiano  
<v0k0ng$kiku$1@dont-email.me>

View for Bookmarking (what is this?)
Look up another Usenet article

Path: ...!weretis.net!feeder9.news.weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: Don Y <blockedofcourse@foo.invalid>
Newsgroups: sci.electronics.design
Subject: Anticipating processor architectural evolution
Date: Sat, 27 Apr 2024 16:11:30 -0700
Organization: A noiseless patient Spider
Lines: 23
Message-ID: <v0k0ng$kiku$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Sun, 28 Apr 2024 01:11:46 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="c979a7d194ef94c5c3a16b2d276e357d";
	logging-data="674462"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1/S7kggKsYBlPreTbu9dsd3"
User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101
 Thunderbird/102.2.2
Cancel-Lock: sha1:kIvReDCDcVYIbo4f2fIuUBFOQ+U=
Content-Language: en-US
Bytes: 2027

I've had to refactor my RTOS design to accommodate the likelihood of SMT
in future architectures.

Thinking (hoping?) these logical cores to be the "closest to the code",
I call them "Processors" (hysterical raisins).  Implicit in SMT is the
notion that they are architecturally similar/identical.

These are part of PHYSICAL cores -- that I appropriately call "Cores".

These Cores are part of "Hosts" (ick; term begs for clarity!)... what
one would casually call "chips"/CPUs.  Note that a host can house dissimilar
Cores (e.g., big.LITTLE).

Two or more hosts can be present on a "Node" (the smallest unit intended to
be added to or removed from a "System").  Again, they can be dissimilar
(think CPU/GPU).

I believe this covers the composition/hierarchy of any (near) future
system architectures.  And, places the minimum constraints on said.

Are there any other significant developments in the pipeline that
could alter my conception of future hardware designs?