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Path: ...!3.eu.feeder.erje.net!feeder.erje.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Thomas Koenig <tkoenig@netcologne.de> Newsgroups: comp.arch Subject: Re: architecture, The Design of Design Date: Sun, 5 May 2024 10:50:34 -0000 (UTC) Organization: A noiseless patient Spider Lines: 33 Message-ID: <v17o9q$1qgti$1@dont-email.me> References: <v03uh5$gbd5$1@dont-email.me> <c4ee3c91e9a05dee1098a3786edb61df@www.novabbs.org> <v0rhqv$1itj$3@gal.iecc.com> <86r0emt69e.fsf@linuxsc.com> <v0tuqt$613$2@gal.iecc.com> <v10e7r$3ultn$1@dont-email.me> <B1TYN.55142$gF_b.20839@fx17.iad> Injection-Date: Sun, 05 May 2024 12:50:34 +0200 (CEST) Injection-Info: dont-email.me; posting-host="e695b989a3c9c61b31a2cf887bddb8f7"; logging-data="1917874"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ULdC3wpmI5cmbp3Ys4N72uUSSy7y5IhA=" User-Agent: slrn/1.0.3 (Linux) Cancel-Lock: sha1:mcqfQzOza6PztYMOurnOVouCX3k= Bytes: 2579 EricP <ThatWouldBeTelling@thevillage.com> schrieb: > https://computermuseum.uwaterloo.ca/index.php/Detail/objects/13 > > and says the 704 tube logic circuits were designed by someone named > A. Halsey Dickinson, AND it seems he also designed the 604 tube circuits, > which were circa 1948, and those are documented. > This document is dated 1958 so contemporaneous with the 704 > and details the 604 tube logic circuits: > > http://www.bitsavers.org/pdf/ibm/604/227-7609-0_604_CE_man_1958.pdf > > It is possible the 704's "T" gate stands for what 604 called TR or > Trigger units, which appears to be what we today call an SR Latch. Quite interesting. They had inverter, two-input NAND, two-input NOR, Pentagrid as a two-input OR, and a cheap Diode Switch (DS) as two-input AND) as logic gates. The 704 seems to have used mostly AND and OR gates, so the decision to AND the index register with the bit from the instruction and then OR them together actually seems straightforward, this also gives you zero if none of them is selected. Having the possibility of more than one index register seems to have been a consequence of design which allowed for zero or the content of one register as the main purpose. Even if no documents survive to prove this, I'm fairly confident that this is why they did it. Programmers being programmers, they probably started using the feature for some multi-dimensional arrays with sizes of powers of two, and IBM was then stuck with the feature.