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From: Terje Mathisen <terje.mathisen@tmsw.no>
Newsgroups: comp.arch
Subject: Re: Making Lemonade (Floating-point format changes)
Date: Mon, 20 May 2024 09:24:16 +0200
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Michael S wrote:
> On Sun, 19 May 2024 18:37:51 +0200
> Terje Mathisen <terje.mathisen@tmsw.no> wrote:
> 
>> Thomas Koenig wrote:
>>> So, I did some more measurements on the POWER9 machine, and it came
>>> to around 18 cycles per FMA.  Compared to the 13 cycles for the
>>> FMA instruction, this actually sounds reasonable.
>>>
>>> The big problem appears to be that, in this particular
>>> implementation, multiplication is not pipelined, but done by
>>> piecewise by addition.  This can be explained by the fact that
>>> this is mostly a decimal unit, with the 128-bit QP just added as
>>> an afterthought, and decimal multiplication does not happen all
>>> that often.
>>>
>>> A fully pipelined FMA unit capable of 128-bit arithmetic would be
>>> an entirely different beast, I would expect a throughput of 1 per
>>> cycle and a latency of (maybe) one cycle more than 64-bit FMA.
>>>    
>> The FMA normalizer has to handle a maximally bad cancellation, so it
>> needs to be around 350 bits wide. Mitch knows of course but I'm
>> guessing that this could at least be close to needing an extra cycle
>> on its own and/or heroic hardware?
>>
>> Terje
>>
> 
> Why so wide?
> Assuming that subnormal multiplier inputs are normalized before

They are not, this is part of what you do to make subnormal numbers 
exactly the same speed as normal inputs.

Terje

-- 
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"