Path: ...!news.mixmin.net!news.neodome.net!rocksolid2!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Fri, 3 May 2024 19:04:19 +0000
Organization: Rocksolid Light
Message-ID: <f9a71858ed2d81f062c2df01cac14fe8@www.novabbs.org>
References: <v0s17o$2okf4$2@dont-email.me> <v0s744$l3v$1@gal.iecc.com> <v0snlh$30rmc$2@dont-email.me> <v0u95n$1oje$1@gal.iecc.com> <v0uihh$3e0vg$5@dont-email.me> <9ef6b3ccf22295ffa50de9ec20623d92@www.novabbs.org> <v11u92$cghm$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="3155304"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A";
User-Agent: Rocksolid Light
X-Spam-Checker-Version: SpamAssassin 4.0.0
X-Rslight-Site: $2y$10$YqufmvekvIREU.WajBobceaMWL0OUqR3gWSOVcDmNjeKVICZwMVOa
X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8
Bytes: 2613
Lines: 55

Lawrence D'Oliveiro wrote:

> On Thu, 2 May 2024 18:33:48 +0000, MitchAlsup1 wrote:

>> Lawrence D'Oliveiro wrote:
>> 
>>>     move.l a, b
>>>     move.b b, c
>> 
>> May I suggest that the above ILLUSTRATES why someone wants to use LD
and
>> ST instructions rather than directionless MOV instructions.

> OK, use explicit load/store instead of generic move:

> register-memory-register:

>     store.l a, b
>     load.b  b, c

> memory-register-memory:

>     load.l  a, b
>     store.b b, c

> Do you see why this makes absolutely no difference to what happens, as
per 
> my description earlier?

Yes, because you explicitly left out the syntactic sugar.

Try::

     STD    R7,[IP,#192]
     LDSB   R8,[SP,#32]

See, by having the syntactic sugar to identify which is the register
and which is the address and what direction the data is traveling,
all the confusion goes away.

The OpCode tells the direction LD is inbound, ST is outbound..
The operand with the 'R' is the register
The operand with the '[' and ']' is the address.

> By the way, in case it wasn’t clear: in my examples, the destination 
> operand is always the last one.

My preference is that the address operands are always in the same spot in 
the instruction, and that the destination register is the receiver of a
LD and the sender of the ST.

And secondly, the destination is written like one writes assignments::

     R9 = memory( pointer, index, offset );
or
     R8 = R8 + #32