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From: Terje Mathisen <terje.mathisen@tmsw.no>
Newsgroups: comp.arch
Subject: Re: Privilege Levels Below User
Date: Mon, 10 Jun 2024 18:52:06 +0200
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EricP wrote:
[snip]
> Many processors automatically disable interrupts on trap because it
> greatly simplifies the race conditions in their prologue and epilogue.
> x86 did not disable interrupts on exceptions but x64 allows it as an 
> option.

I have written a lot of x86 interrupt handlers, these chips did very 
much disable all interrupts when transferring control to my handler.

The typical approach was to do the minimum work possible to save 
whatever HW buffer/data needed saving, before executing a STI (SeT 
Interrupt enable bit?) and then do anything else that had to be done 
while still in the primary handler.

IRET restored flags, IP and CS, transferring control back to whatever 
was running when the hw interrupt happened.

Terje


-- 
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"