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From: olcott <polcott333@gmail.com>
Newsgroups: comp.theory,sci.logic
Subject: Re: Liar detector: Fred, Richard, Joes and Alan --- Ben's agreement
Date: Sat, 6 Jul 2024 10:10:06 -0500
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On 7/6/2024 10:00 AM, Fred. Zwarts wrote:
> Op 06.jul.2024 om 15:01 schreef olcott:
>> On 7/6/2024 4:09 AM, Fred. Zwarts wrote:
>>> Op 05.jul.2024 om 17:54 schreef olcott:
>>>> On 7/5/2024 10:48 AM, Fred. Zwarts wrote:
>>>>> Op 05.jul.2024 om 16:05 schreef olcott:
>>>>>> On 7/5/2024 8:54 AM, Fred. Zwarts wrote:
>>>>>>>
>>>>>>> HHH cannot possibly correctly simulate itself.
>>>>>>>
>>>>>> LIAR! I give up on you.
>>>>>> https://liarparadox.org/HHH(DDD)_Full_Trace.pdf
>>>>>
>>>>> No need to come back, because you are unable to point to any error 
>>>>> in my reasoning. 
>>>>
>>>> I conclusively proved that HHH is correctly simulating itself
>>>> simulating DDD and you simply freaking lie about it.
>>>>
>>>>> Your replies are only irrelevant, or supporting my reasoning. I 
>>>>> showed that HHH cannot possibly simulate itself correctly and your 
>>>>> full trace supports this, as it shows that the simulating HHH is 
>>>>> unable to reach the 'ret' of the simulated HHH.
>>>>>
>>>>
>>>> *Unable to reach ret IS A FREAKING CORRECT FREAKING SIMULATION*
>>>
>>> Unable to reach ret *is a freaking demonstration* of an incorrect 
>>> simulation.
>>>
>>
>> If it was incorrect you would have to show which
>> x86 instruction was simulated incorrectly. You
>> can't do that because it is a matter of verified
>> fact that none of them were simulated incorrectly.
> 
> Incorrect reasoning. 

I commented at the wrong place.

The semantics of the x86 language are the only criterion
measure of correct emulation. Only stupid liars would disagree.

Smart liars would not disagree because they would know how
stupid this makes them look. Smart liars would disagree on
much more subtle things.

> Is it really over your head? The simulated 
> instructions are correct, but the instructions that are not simulated 
> make the simulation incorrect. The simulation is aborted too soon. One 
> cycle later the simulated HHH would abort and halt. That part of the 
> input is neglected by your simulation, which makes it incorrect, because 
> it should process the whole input, not only the first part.
> 
>>
>>>> The machine code specifies that DDD simulated by HHH according
>>>> to the semantics of the x86 language cannot possibly reach the
>>>> ret instruction of DDD or its correctly simulated self.
>>>>
>>>> _DDD()
>>>> [00002172] 55               push ebp      ; housekeeping
>>>> [00002173] 8bec             mov ebp,esp   ; housekeeping
>>>> [00002175] 6872210000       push 00002172 ; push DDD
>>>> [0000217a] e853f4ffff       call 000015d2 ; call HHH(DDD)
>>>> [0000217f] 83c404           add esp,+04
>>>> [00002182] 5d               pop ebp
>>>> [00002183] c3               ret
>>>> Size in bytes:(0018) [00002183]
>>>>
>>>>
>>>
>>> Your traces shows that HHH aborts the simulation at a point there the 
>>> simulated HHH has only one cycle to go before it would abort and halt. 
>>
>> All of the HHH have the same code. The outer HHH
>> meets its abort criteria first. It is a verified
>> fact that unless the outer HHH aborts then none
>> of them do. This violates this correct criteria
> 
> Incorrect reasoning.
> Dreaming of an HHH that does not abort is irrelevant. This HHH *does* 
> abort. The outer one does, so all of them do. Therefore, the HHH 
> simulated by the outer one is aborted one cycle before it would abort 
> and halt, as well. That makes the abort premature.
> HHH cannot possibly simulate itself correctly.
> 
>>
>> <MIT Professor Sipser agreed to ONLY these verbatim words 10/13/2022>
>>      If simulating halt decider H correctly simulates its input D
>>      until H correctly determines that its simulated D would never
>>      stop running unless aborted then
>>
>>      H can abort its simulation of D and correctly report that D
>>      specifies a non-halting sequence of configurations.
>> </MIT Professor Sipser agreed to ONLY these verbatim words 10/13/2022>
>>
> 
> Incorrect reasoning.
> You forget pretty soon you have been told many times that Sipser does 
> not apply here. You keep repeating this irrelevant text. It is 
> irrelevant, because it is about a correct simulation, not about an 
> incorrect simulation.
> 
>>> So, the only reason why this simulation does not reach the 'ret' of 
>>> the simulated HHH, is that it is aborted prematurely.
>>> A correct simulation by another simulator shows that this is indeed 
>>> the case.
>>
>> HHH1 can wait for HHH to abort because DDD does not call HHH1.
>> HHH cannot wait because DDD calls HHH.
>>
>>> HHH cannot possible simulate *itself* correctly. This code and your 
>>> trace demonstrates this. The fact that the simulation does not reach 
>>> the 'ret', where other simulator can do that, demonstrates that HHH's 
>>> simulation of itself is incorrect.
>>>
>>> The only thing you brought in against it, is a baseless repetition 
>>> that you still belief that the simulation is correct.
>>>
>>> HHH that aborts and halts can be compared to a bear running at you to 
>>> kill you:
>>>
>>> All other simulators will tell you that HHH aborts and halts.
>>> All people will warn you that the bear is running at you and will 
>>> kill you.
>>>
>>> Only when HHH simulates itself, it says: not aborting and non-halting.
>>> The bear says about itself: I am not running and I will not kill you.
>>>
>>> What do you trust?
>>
>> I only trust correct reasoning.
> 
> So, trust my correct reasoning. Not your own incorrect reasoning.
> 

-- 
Copyright 2024 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer