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From: Thomas Koenig <tkoenig@netcologne.de>
Newsgroups: comp.arch
Subject: Re: Continuations
Date: Thu, 18 Jul 2024 15:35:50 -0000 (UTC)
Organization: A noiseless patient Spider
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Michael S <already5chosen@yahoo.com> schrieb:
> On Thu, 18 Jul 2024 13:58:37 GMT
> scott@slp53.sl.home (Scott Lurndal) wrote:
>
>> Michael S <already5chosen@yahoo.com> writes:
>> >On Thu, 18 Jul 2024 06:00:46 -0000 (UTC)
>> >Thomas Koenig <tkoenig@netcologne.de> wrote:
>> >  
>> >> >    
>> >> 
>> >> What about SIMD width underlying the the VVM implementation?
>> >> All SIMD implementations I know of allow performing floating point
>> >> ops in paralell.  Is it planned that My 66000 can also do that?
>> >> (If not, that would be a big disadvantage for scientific/technical
>> >> work).  
>> >
>> >All pre-Merom implementation of SSE2, i.e. Intel Pentium 4, Intel
>> >Pentium-M and AMD K8, do not perform double precision floating point
>> > 
>> 
>> All of which have been obsolete for almost two decades.
>
> According to my understanding, Thomas Koenig was/is around for more
> than three decades.

I have been (starting doing things on mainframes in the late 1980s),
but I was specifically asking about what Mitch had in mind for
My 66000.