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From: Mikko <mikko.levanto@iki.fi>
Newsgroups: comp.theory
Subject: Re: Hypothetical possibilities --- stupid rebuttal
Date: Tue, 30 Jul 2024 09:44:02 +0300
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On 2024-07-29 16:17:32 +0000, olcott said:

> On 7/28/2024 3:04 AM, Mikko wrote:
>> On 2024-07-27 13:55:56 +0000, olcott said:
>> 
>>> On 7/27/2024 1:54 AM, Mikko wrote:
>>>> On 2024-07-26 13:58:54 +0000, olcott said:
>>>> 
>>>>> On 7/26/2024 3:05 AM, Mikko wrote:
>>>>>> On 2024-07-24 13:38:08 +0000, olcott said:
>>>>>> 
>>>>>>> On 7/24/2024 4:01 AM, Mikko wrote:
>>>>>>>> On 2024-07-23 14:41:11 +0000, olcott said:
>>>>>>>> 
>>>>>>>>> On 7/23/2024 2:32 AM, Mikko wrote:
>>>>>>>>>> On 2024-07-22 15:05:41 +0000, olcott said:
>>>>>>>>>> 
>>>>>>>>>>> On 7/22/2024 6:05 AM, Mikko wrote:
>>>>>>>>>>>> On 2024-07-20 15:28:31 +0000, olcott said:
>>>>>>>>>>>> 
>>>>>>>>>>>>> void DDD()
>>>>>>>>>>>>> {
>>>>>>>>>>>>>    HHH(DDD);
>>>>>>>>>>>>> }
>>>>>>>>>>>>> 
>>>>>>>>>>>>> int main()
>>>>>>>>>>>>> {
>>>>>>>>>>>>>    DDD();
>>>>>>>>>>>>> }
>>>>>>>>>>>>> 
>>>>>>>>>>>>> (a) Termination Analyzers / Partial Halt Deciders must halt
>>>>>>>>>>>>> this is a design requirement.
>>>>>>>>>>>> 
>>>>>>>>>>>> For a partial analyzer or deciders this is not always required.
>>>>>>>>>>>> 
>>>>>>>>>>> 
>>>>>>>>>>> *You can't even get my words correctly*
>>>>>>>>>>> A termination analyzer must report on the behavior of at least
>>>>>>>>>>> one input for all of the inputs of this one input. This is
>>>>>>>>>>> met when a termination analyzer analyzes an input having no inputs.
>>>>>>>>>>> 
>>>>>>>>>>> A partial halt decider must correctly determine the halt status
>>>>>>>>>>> of at least one input and its specific input (if any).
>>>>>>>>>>> 
>>>>>>>>>>> HHH is both a partial halt decider and a termination analyzer
>>>>>>>>>>> for DDD and a few other inputs having no input.
>>>>>>>>>>> 
>>>>>>>>>>>>> (b) Every simulating termination analyzer HHH either
>>>>>>>>>>>>> aborts the simulation of its input or not.
>>>>>>>>>>>> 
>>>>>>>>>>>> This must be interpreted to mean that a simulating termination analyzer
>>>>>>>>>>>> may abort its simulation for some simulated abort and simulate others
>>>>>>>>>>>> to the termination.
>>>>>>>>>>>> 
>>>>>>>>>>> 
>>>>>>>>>>> I am talking about hypothetical possible ways that HHH could be encoded.
>>>>>>>>>>> (a) HHH(DDD) is encoded to abort its simulation.
>>>>>>>>>>> (b) HHH(DDD) is encoded to never abort its simulation.
>>>>>>>>>>> 
>>>>>>>>>>>>> (c) Within the hypothetical case where HHH does not abort
>>>>>>>>>>>>> the simulation of its input {HHH, emulated DDD and executed DDD}
>>>>>>>>>>>>> never stop running.
>>>>>>>>>>>> 
>>>>>>>>>>>> The case is not very hypothetical. Given the HHH you already have,
>>>>>>>>>>>> it is fairly easy to construct the "hypothetical" HHH and see what
>>>>>>>>>>>> it actually does.
>>>>>>>>>>>> 
>>>>>>>>>>> 
>>>>>>>>>>> (a) HHH(DDD) is encoded to abort its simulation.
>>>>>>>>>>> (b) HHH(DDD) is encoded to never abort its simulation.
>>>>>>>>>>> 
>>>>>>>>>>>>> This violates the design requirement of (a) therefore HHH must
>>>>>>>>>>>>> abort the simulation of its input.
>>>>>>>>>>>> 
>>>>>>>>>>>> The violation simply means that the "hypothetical" HHH is not a
>>>>>>>>>>>> termination analyzer of partial halt decider in sense (a). What
>>>>>>>>>>>> it "must" be or do depends on the requirements.
>>>>>>>>>>>> 
>>>>>>>>>>> Therefore (a) is correct and (b) is incorrect according to the
>>>>>>>>>>> design requirements for HHH that it must halt.
>>>>>>>>>>> 
>>>>>>>>>>> It is also a truism that any input that must be aborted
>>>>>>>>>>> is a non-halting input.
>>>>>>>>>> 
>>>>>>>>>> No, it is not. The "must" and "non-halting" belong to different worlds.
>>>>>>>>>> The word "must" blongs to requirements. The word "non-halting" is a
>>>>>>>>>> feature of a program. They are unrelated, so one cannot be inferred
>>>>>>>>>> from the other.
>>>>>>>>>> 
>>>>>>>>> 
>>>>>>>>> When-so-ever there are two hypothetical possible way to encode
>>>>>>>>> a simulating halt decider for a specific input
>>>>>>>>> (a) one aborts its simulation of DDD
>>>>>>>>> (b) never aborts its simulation of DDD
>>>>>>>> 
>>>>>>>> Does the simulator that simulates the beginning and end of the
>>>>>>>> simulated computation but skips a part in ghe middle belong to
>>>>>>>> class (a) or class (b)?
>>>>>>>> 
>>>>>>> 
>>>>>>> That is off topic. I am only referring to  a sequence of
>>>>>>> 1 to N x86 machine language instructions simulated according
>>>>>>> to the x86 semantic meaning of these instructions.
>>>>>> 
>>>>>> No, it isn't. Abortion of simulation is a deviation form x86 macine
>>>>>> language semantics. What I ask about does not deviate more.
>>>>> 
>>>>> In other words you are saying that it is absolutely impossible
>>>>> to make an x86 program that is an x86 emulator that correctly
>>>>> emulates a finite number of instructions of non-terminating
>>>>> input x86 machine code.
>>>> 
>>>> You are lying again. That is not the same in other words, and I am
>>>> not saying what you falsely claim.
>>>> 
>>> 
>>> I am not lying I am paraphrasing so that we can come to a mutual
>>> understanding.
>> 
>> It is lying to paraphrase so that the original meaning is not preserved.
>> 
> 
> I make my point mere clearly here:
> [Any honest person that knows the x86 language can see...]

That does not alter the fact that you lied above. Therefore the term
"honest person" does not include you. So what is your evidence that
any (or even some) honest person can see...?

-- 
Mikko