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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: Arguments for a sane ISA 6-years later
Date: Tue, 30 Jul 2024 13:56:03 -0700
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On 7/30/2024 1:23 PM, BGB wrote:
> On 7/30/2024 4:44 AM, Anton Ertl wrote:
>> BGB <cr88192@gmail.com> writes:
>>> Otherwise, stuff isn't going to fit into the FPGAs.
>>>
>>> Something like TSO is a lot of complexity for not much gain.
>>
>> Given that you are so constrained, the easiest corner to cut is to
>> have only one core.  And then even seqyential consistency is trivial
>> to implement.
>>
> 
> On the XC7A100T, this is what I am doing...
> 
> With the current feature-set, don't have enough resource budget to go 
> dual core at present.
> 
> I can go dual core on the Xc7A200T though.
> 
> 
> 
> Granted, one could argue that maybe one should not do such an elaborate 
> CPU. Say, a case could be made for just doing a RISC-V implementation.
> 
> There is an RV32GC implementation (dual-issue superscalar) that can run 
> on the XC7A100T that, ironically, still takes most of the FPGA and can 
> only run at ~ 25 or 33 MHz. Its IPC is pretty good, but it runs at a low 
> clock-speed and is 32-bit.
> 
> Only real way to make small/fast cores though is to make them 
> single-issue and limit the feature-set (only doing a basic integer ISA).
[...]

Have you ever messed around with a Cell processor? Think of its vector 
processing units, or Synergistic Processing Elements (SPE) iirc. Also, 
iirc it was not that easy to program for. buffered DMA wrt the SPE's, 
again iirc. So, some games only used the "single" PPE unit. Iirc, they 
wanted more PPE units but that was not realized...