Deutsch English Français Italiano |
<v8gn0c$2b8r9$1@dont-email.me> View for Bookmarking (what is this?) Look up another Usenet article |
Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Buzz McCool <buzz_mccool@yahoo.com> Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.arch.embedded Subject: Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Date: Thu, 1 Aug 2024 12:17:32 -0700 Organization: A noiseless patient Spider Lines: 11 Message-ID: <v8gn0c$2b8r9$1@dont-email.me> References: <5ccd7c07-93d6-424d-909b-b13ebe6cf1f2n@googlegroups.com> <8fd3081d-4977-c809-2c81-c200605ac323@insomnia247.nl> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 01 Aug 2024 21:17:32 +0200 (CEST) Injection-Info: dont-email.me; posting-host="6014bda7f48739ee4d3a5e70475d10a6"; logging-data="2466665"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19VXmWnpq9g+TL0RVYsBOqBVvm8j4ngpFo=" User-Agent: Mozilla Thunderbird Cancel-Lock: sha1:QOTYpgcAHrsv00KiZCVskrJ1uhw= In-Reply-To: <8fd3081d-4977-c809-2c81-c200605ac323@insomnia247.nl> Content-Language: en-US Bytes: 1783 On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote: > I found that the overwhelming majority of the Internet's solution to > slowing down a fast clock (for making the pulsing of an LED visible to > the human eye) was either using vendor-specific, proprietary clock > managers and PLLs or implementing some twenty-something-bit-wide counter > as to count hundreds of thousands of clock cycles and generate a 1 Hz > output. If you did not have access to FPGA shift register primitives, what would be the most efficient way to build a prescaler from discrete parts?