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From: Buzz McCool <buzz_mccool@yahoo.com>
Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.arch.embedded
Subject: Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using
 Cascading Shift Registers
Date: Thu, 1 Aug 2024 12:17:32 -0700
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On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote:
> I found that the overwhelming majority of the Internet's solution to 
> slowing down a fast clock (for making the pulsing of an LED visible to 
> the human eye) was either using vendor-specific, proprietary clock 
> managers and PLLs or implementing some twenty-something-bit-wide counter 
> as to count hundreds of thousands of clock cycles and generate a 1 Hz 
> output.

If you did not have access to FPGA shift register primitives, what would 
be the most efficient way to build a prescaler from discrete parts?