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From: Dimiter_Popoff <dp@tgi-sci.com>
Newsgroups: sci.electronics.design
Subject: Re: Intel
Date: Mon, 5 Aug 2024 00:47:59 +0300
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On 8/4/2024 1:54, Gerhard Hoffmann wrote:
> Am 03.08.24 um 23:52 schrieb Phil Hobbs:
>> On 2024-08-03 17:47, John Larkin wrote:
>>> On Sat, 03 Aug 2024 17:18:33 -0400, Joe Gwinn <joegwinn@comcast.net>
>>> wrote:
>>>
>>>> On Sat, 03 Aug 2024 12:32:23 -0700, John Larkin
>>>> <jjlarkin@highlandtechnology.com> wrote:
>>>>
>>>>> https://www.nextplatform.com/2024/08/02/the-resurrection-of-intel-will-take-more-than-three-days/?td=rt-3a
>>>>>
>>>>> Looks like they wrecked Altera.
> 
> Altera was founded with Intel money, and the Intel Eprom process.
> Remember the EP300?
> 
>>>> And hung onto the Intel '86 architecture a tad too tightly, for far
>>>> too long.
> 
> In the last 20 years, Intel processors had nothing to do with the x86
> architecture, except that they could accept x86 code after reset.
> Inside, they are a bunch of RISCs, and there is no EAX register but
> some 100s of renaming registers that all could take the role of EAX,
> in case of speculative execution even some of them at the same time.

So do they have any instruction set available to the programmer other
than the x86 one or is all this just an emulation of x86 code.
Is there a programming model to be seen in some public document
describing all those many registers. Last time I (vaguely) checked
all I could see were the x86 registers, just made longer - which
brings with itself all the limitations the x86 architecture has
always had, just going over them faster by faster silicon.