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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: Arguments for a sane ISA 6-years later
Date: Mon, 5 Aug 2024 19:30:51 -0700
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On 7/26/2024 10:00 AM, Anton Ertl wrote:
> "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:
>> On 7/25/2024 1:09 PM, BGB wrote:
>>> At least with a weak model, software knows that if it doesn't go through
>>> the rituals, the memory will be stale.
> 
> There is no guarantee of staleness, only a lack of stronger ordering
> guarantees.
> 
>> The weak model is ideal for me. I know how to program for it
> 
> And the fact that this model is so hard to use that few others know
> how to program for it make it ideal for you.
> 
>> and it's more efficient
> 
> That depends on the hardware.
> 
> Yes, the Alpha 21164 with its imprecise exceptions was "more
> efficient" than other hardware for a while, then the Pentium Pro came
> along and gave us precise exceptions and more efficiency.  And
> eventually the Alpha people learned the trick, too, and 21264 provided
> precise exceptions (although they did not admit this) and more
> efficieny.
[...]

Iirc, the Alpha requires a memory barrier even for RCU because, iirc, it 
does not honor data dependent loads... These are a no-op on most archs, 
but Alpha, well, nope!