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Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Lawrence D'Oliveiro <ldo@nz.invalid> Newsgroups: comp.arch Subject: Instruction Tracing Date: Sat, 10 Aug 2024 06:20:51 -0000 (UTC) Organization: A noiseless patient Spider Lines: 26 Message-ID: <v970s3$flpo$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 10 Aug 2024 08:20:51 +0200 (CEST) Injection-Info: dont-email.me; posting-host="0cdcc95047601bfdd95c13b1efe74c93"; logging-data="513848"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19a3Fkg3eERC2VazADu9X5I" User-Agent: Pan/0.159 (Vovchansk; ) Cancel-Lock: sha1:j+yAurFryq/ZYO5WULWafmQFiB4= Bytes: 2233 In the early days of the spread of RISC (i.e. the 1980s), much was made of the analysis of the dynamic execution profiles of actual compiled programs to see what machine instructions they most frequently used. This then became the rationale for optimizing common instructions, and even omitting ones that were not so often used. One thing these instruction traces would frequently report is that integer multiply and divide instructions were not so common, and so could be omitted and emulated in software, with minimal impact on overall performance. We saw this design decision taken in the early versions of Sun’s SPARC for example, and also IBM’s ROMP as used in the RT PC. Later, it seems, the CPU designers realized that instruction traces were not the final word on performance measurements, and started to include hardware integer multiply and divide instructions. (ROMP was also one of those RISC architectures that had delayed branches, along with MIPS, HP-PA and I think SPARC as well.) I have heard it said that the RT PC was a poor advertisement for the benefits of RISC, and the joke was made that “RT” stood for “Reduced Technology”. Later, of course, IBM more than made good this deficiency with its second take on RISC, in the form of the POWER architecture, which is still a performance leader to this day.