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From: Lawrence D'Oliveiro <ldo@nz.invalid>
Newsgroups: comp.arch
Subject: Re: Instruction Tracing
Date: Sun, 11 Aug 2024 23:07:03 -0000 (UTC)
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On Sun, 11 Aug 2024 14:44:38 GMT, Anton Ertl wrote:

> Power (IIRC) and Alpha don't have delayed branches.

Not only does POWER not have delayed branches, but I recall the IBM folks 
claiming in the initial publicity that branches could often execute in 
zero clock cycles--that is, fully overlapped with surrounding 
instructions.

POWER was also “superscalar” (being able to execute more than one 
operation per clock cycle) right from the beginning. Not sure if other 
RISC architectures of the time were like that. I don’t think Alpha was: 
one thing I remember from its early descriptions was its use of very high 
clock speeds. That seemed to me to be the opposite of “(at least) one 
instruction per clock cycle”, which I thought was supposed to be one of 
the defining features of RISC.