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From: Lawrence D'Oliveiro <ldo@nz.invalid>
Newsgroups: comp.arch
Subject: Re: Instruction Tracing
Date: Mon, 12 Aug 2024 08:42:51 -0000 (UTC)
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On Mon, 12 Aug 2024 11:09:18 +0300, Michael S wrote:

> On Mon, 12 Aug 2024 06:33:17 -0000 (UTC)
> Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
> 
>> But in spite of having, say, 2½ times the clock speed of POWER, Alpha
>> was not 2½ times faster, was it?
> 
> Of course not.

That’s what I mean: it took several clock cycles per instruction, contrary 
to just about every other RISC architecture.