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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Don Y <blockedofcourse@foo.invalid> Newsgroups: comp.arch.embedded Subject: Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Date: Tue, 13 Aug 2024 12:24:21 -0700 Organization: A noiseless patient Spider Lines: 32 Message-ID: <v9gbt7$1gkt$2@dont-email.me> References: <5ccd7c07-93d6-424d-909b-b13ebe6cf1f2n@googlegroups.com> <8fd3081d-4977-c809-2c81-c200605ac323@insomnia247.nl> <v8gn0c$2b8r9$1@dont-email.me> <v9gbr0$1gkt$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 13 Aug 2024 21:24:24 +0200 (CEST) Injection-Info: dont-email.me; posting-host="4b843f87e9104d6aeb11fe70e53c0996"; logging-data="49821"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xOkrVVHjIgmr3E9kJTZWF" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Cancel-Lock: sha1:OYqKeB3sE44EYdd8LoZ2GHxpcpE= Content-Language: en-US In-Reply-To: <v9gbr0$1gkt$1@dont-email.me> Bytes: 2704 On 8/13/2024 12:23 PM, Don Y wrote: > On 8/1/2024 12:17 PM, Buzz McCool wrote: >> On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote: >>> I found that the overwhelming majority of the Internet's solution to slowing >>> down a fast clock (for making the pulsing of an LED visible to the human >>> eye) was either using vendor-specific, proprietary clock managers and PLLs >>> or implementing some twenty-something-bit-wide counter as to count hundreds >>> of thousands of clock cycles and generate a 1 Hz output. > > That depends on what you want to use to "trigger" the LED's illumination. > Monostables (in many forms) can generate an interval that is "close enough > for the purposes of human perception" with very little (if ANY!) silicon. > >> If you did not have access to FPGA shift register primitives, what would be >> the most efficient way to build a prescaler from discrete parts? > > How do you define "efficient"? > > Shift counters are incredibly simple with the drawback of front-loading > all of the combinatorial logic. Certain divisors are, thus, more costly > than others. > > Binary ripple counters use the least resources but suffer from > propagation delays making decoding of states a bit trickier. > > You will always need at least log2N flip-flops and could end up > using slightly more. [Of course, the c.a.e solution would be a 6 pin MCU counting time in software]