Path: ...!3.eu.feeder.erje.net!feeder.erje.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: BGB <cr88192@gmail.com>
Newsgroups: comp.arch
Subject: Re: My 66000 and High word facility
Date: Wed, 14 Aug 2024 05:24:50 -0500
Organization: A noiseless patient Spider
Lines: 41
Message-ID: <v9i0lm$dmsd$2@dont-email.me>
References: <v98asi$rulo$1@dont-email.me>
 <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org>
 <v991kh$vu8g$1@dont-email.me> <2024Aug11.163333@mips.complang.tuwien.ac.at>
 <v9ath5$2qgnb$1@dont-email.me> <2024Aug12.082936@mips.complang.tuwien.ac.at>
 <130df049c4c97984986767736b5b037a@www.novabbs.org>
 <v9dnmv$3efnj$1@dont-email.me>
 <acb76cee233f19672f2ad0380c9cd06e@www.novabbs.org>
 <v9dt2a$3fdml$1@dont-email.me>
 <27b9630c6cd23b6ac1251bb3416ce1cf@www.novabbs.org>
 <v9e9nk$3i0qi$1@dont-email.me>
 <d491513fc46ed375dd1d3764dbdf9b6f@www.novabbs.org>
 <v9el5h$3njmh$1@dont-email.me>
 <cf020629e85ce690b8d60d92cea9023e@www.novabbs.org>
 <v9gbn0$1jge$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Wed, 14 Aug 2024 12:24:55 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="563ca555b98437b11192305ee437d070";
	logging-data="449421"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX198Bdfqys/5GgW1rdTmnffUG8WDq22WM0U="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:mhl5rAwnLy5n8of07pmrkIfFIk8=
Content-Language: en-US
In-Reply-To: <v9gbn0$1jge$1@dont-email.me>
Bytes: 3085

On 8/13/2024 2:21 PM, Thomas Koenig wrote:
> MitchAlsup1 <mitchalsup@aol.com> schrieb:
> 
>> Anybody claiming RISC-V has a good ISA should have their degree revoked.
> 
> Interesting datapoint: In the GhostWrite paper, they say that 84.03%
> of the RISC-V instruction space are taken up.
> 
> I could probably gather the same statistic for My 66000...


In my case:
   F0: ~%88%, drops to ~75% if reclaiming the deprecated BT/BF ops.
   F1: ~100% used (Ld/St Disp, CompareBranch).
   F2: 3RI (Imm9) ~100%, 2RI (Imm10) ~50%
   F3: 0%
   F8: 2RI Imm16 ~75%
   F9: 0%

The F3 and F9 blocks would follow a similar pattern to the F0 block.

Current thinking was that much or all of F3 would potentially be used 
for dynamically assigned instruction blocks rather than static assigned 
encodings. These blocks would likely be assigned per-task (by loading 
block selector magic numbers into a register, which is then used by the 
decoder).

Around 90% or so if excluding F3 and F9,
Drops to around 59% used if the F3 and F9 blocks are counted...



Note that F4/F5/F6/F7 and FA/FB/FC/FD/FE/FF are non-assignable.
If a mode were added that disallowed WEX encodings, it is possible that 
F4..F7 and FC/FD could be reclaimed (as-is, they mirror existing blocks).


However, the rate of adding new instructions has dropped off as I seem 
to be nearing a point where "meaningful additions" are becoming rarer.