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From: Brett <ggtgp@yahoo.com>
Newsgroups: comp.arch
Subject: Banked register files
Date: Mon, 19 Aug 2024 21:46:07 -0000 (UTC)
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Banked register files, a mental exercise at expanding the register file.

With three operand RISC you have you have three 5 bit register specifiers
using 15 bits.

If instead you have eight banks of eight registers you have a 3 bit bank
specifier and three 3 bit register specifiers for 12 bits. 

Now the banks need to talk to each other and so you would add a bit to each
register specifier to tell whether it uses the bank or the base registers,
for 72 registers total, not 64. So a 3 bit bank specifier and three 4 bit
register specifiers for 15 bits, the same as a 32 register RISC chip.

Two operand plus 16 bit offset instructions would need to sacrifice one bit
of offset. Four operand instructions would save a bit. 

As an extra bonus you now have another 3 bit field that could be another
source or destination if you are not using the bank register. But with only
eight base registers it can look hard to pull off using 4 or 5 registers at
once. But maybe not if most of the addressing is in the bank registers. The
frame pointer would be in the base registers, as it loads the other
pointers.

The most general case for banked registers is loop unrolling. Eight
registers is not a lot so the first loop may use two banks, but now you
have 4 unrolls that are fairly trivial to set up.

Is this a good idea, maybe, maybe not. This is a mental exercise, it proves
I am mental. ;)

How does banked compare to high registers? Not as good. 

Intel could pull off something like this to one up ARM. A new fixed width
instruction set with a nice patent moat, and fits the x86 mindset.