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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Brett <ggtgp@yahoo.com> Newsgroups: comp.arch Subject: Re: My 66000 and High word facility Date: Mon, 19 Aug 2024 23:35:54 -0000 (UTC) Organization: A noiseless patient Spider Lines: 48 Message-ID: <va0ksq$32gul$1@dont-email.me> References: <v98asi$rulo$1@dont-email.me> <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org> <v991kh$vu8g$1@dont-email.me> <e4352bad7240a6276e453226136ea0b3@www.novabbs.org> <va049n$2vnr7$1@dont-email.me> <a566ca0c8b5c41f402b60e8bac445e24@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Aug 2024 01:35:55 +0200 (CEST) Injection-Info: dont-email.me; posting-host="d70a99a3390f4a82bea332449318e856"; logging-data="3228629"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/zaT6nEsAiFbAEUVFXSOLB" User-Agent: NewsTap/5.5 (iPad) Cancel-Lock: sha1:DuiomhaHxmIYwHAqawmKZeQa/w8= sha1:8O0ZIruUbSLgtdpsvIgSS0ZONdk= Bytes: 3167 MitchAlsup1 <mitchalsup@aol.com> wrote: > On Mon, 19 Aug 2024 18:52:39 +0000, Brett wrote: > >> MitchAlsup1 <mitchalsup@aol.com> wrote: >>> On Sun, 11 Aug 2024 0:46:09 +0000, Brett wrote: >>> >>> >>> The thing is that one you go down the GBOoO route, your lack of >>> registers >>> "namable in ASM" ceases to become a performance degrader. With renaming >>> one can have R7 in use 40 times in a 100 instruction deep execution >>> window. >> >> If this was true we would have 16 or even 8 visible registers, and all >> would be fine. x86 does mostly fine with 16, of course x84 had fab and >> cubic dollar advantages that dwarfed the register limit. > > Careful, here:: > > x86 has LD-OPs and LD-OP-STs which makes the 16 register file feel more > like it has 20-22 registers. Do not underestimate this phenomenon. The > gain from 16-32 registers is only 3%-ish so one would estimate that 22 > registers would have already gained 1/2 of all of what is possible. > >> 64 separate registers was a bridge to far, but it was an interesting >> exercise before it crashed and burned due to the bits being not quite >> available. So close, yet so far. I could not make it work. > > We remain hobbled by the definition of Byte containing exactly 8-bits. > It is this which drives the 16-bit and 32-bit instruction sizes; and > it is this which drives the sizes of constants used by the instruction > stream. > > 64 registers makes PERFECT sense in a 36-bit (or 72-bit) architecture. > But we must all face facts:: > a) Little Endian Won > b) 8-bit Bytes Won > c) longer operands are composed of multiple bytes mostly powers of 2. > d) otherwise it is merely an academic exercise. > If you pack 7 instructions in 8 long words that gives you an extra nibble, 4 bits. You can do lots of four operand dual operations, which may get you back the code density lost, while improving performance. 3 instructions packed in 4 longs gives 64 registers plus four operand dual instructions.