Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: Stephen Fuld <sfuld@alumni.cmu.edu.invalid>
Newsgroups: comp.arch
Subject: Re: number of registers
Date: Wed, 21 Aug 2024 10:20:07 -0700
Organization: A noiseless patient Spider
Lines: 40
Message-ID: <va57k7$1uo38$2@dont-email.me>
References: <v98asi$rulo$1@dont-email.me> <v991kh$vu8g$1@dont-email.me>
 <e4352bad7240a6276e453226136ea0b3@www.novabbs.org>
 <va049n$2vnr7$1@dont-email.me>
 <a566ca0c8b5c41f402b60e8bac445e24@www.novabbs.org>
 <2024Aug20.090149@mips.complang.tuwien.ac.at>
 <a3a57791722f7c21c4218f5be6226e97@www.novabbs.org>
 <20240820204050.00003d56@yahoo.com>
 <48438024ccdbcc373e4cfa51d18066f5@www.novabbs.org>
 <2024Aug21.121312@mips.complang.tuwien.ac.at> <va529m$1uo39$1@dont-email.me>
 <2024Aug21.184537@mips.complang.tuwien.ac.at>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Wed, 21 Aug 2024 19:20:07 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="3e6a1e730eaf8f568c20cfe9a6f00305";
	logging-data="2056296"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1/sEv8JRZPSA4Brz94dTg+2MYQOAv1mou0="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:v69qyEyfu0spkTCn3jA2eaNY99A=
Content-Language: en-US
In-Reply-To: <2024Aug21.184537@mips.complang.tuwien.ac.at>
Bytes: 3238

On 8/21/2024 9:45 AM, Anton Ertl wrote:
> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>> There are also some savings in reduced I-cache usage (possibly leading
>> to higher I-cache hit rate), reduced memory I-fetch memory bandwidth
>> required, etc, though these may be modest at best.
> 
> Let's see how that works out.  I am using the code size numbers
> from <2024Jan4.101941@mips.complang.tuwien.ac.at>:
> 
>     bash     grep      gzip
>    595204   107636    46744 armhf    16 regs load/store     32-bit
>    599832   101102    46898 riscv64  32 regs load/store     64-bit
>    796501   144926    57729 amd64    16 regs ld-op ld-op-st 64-bit
>    829776   134784    56868 arm64    32 regs load/store     64-bit
>    853892   152068    61124 i386      8 regs ld-op ld-op-st 32-bit
>    891128   158544    68500 armel    16 regs load/store     32-bit
>    892688   168816    64664 s390x    16 regs ld-op ld-op-st 64-bit
>   1020720   170736    71088 mips64el 32 regs load/store     64-bit
>   1168104   194900    83332 ppc64el  32 regs load/store     64-bit
> 
> So the least code size is from a load/store architecture with 16
> registers, followed (or preceded in the case of grep) by a load/store
> architecture with 32 registers.  The instruction sets that have
> loap-op and load-op-st instructions result in bigger code. 

Interesting, thanks.


> The
> different sizes of armhf (ARMv7) and armel (ARMv4t-ARMv6t) show that
> there is more to code sizes than just the architecture.

Certainly.   It would take a more detailed analysis (that I am not 
capable of), to determine all the causes of the results you show.



-- 
  - Stephen Fuld
(e-mail address disguised to prevent spam)