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From: BGB <cr88192@gmail.com>
Newsgroups: comp.arch
Subject: Re: Computer architects leaving Intel...
Date: Fri, 30 Aug 2024 17:42:19 -0500
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On 8/30/2024 1:11 PM, MitchAlsup1 wrote:
> On Thu, 29 Aug 2024 19:07:29 +0000, BGB wrote:
> 
>> On 8/29/2024 11:23 AM, MitchAlsup1 wrote:
>>>>>>
>>>>> Time to up your game to an industrial quality ISA.
>>>>
>>>> Open question of what an "industrial quality" ISA has that BJX2 
>>>> lacks...
>>>>    Limiting the scope to things that RISC-V and ARM have.
>>>
>>> Proper handling of exceptions (ignoring them is not proper)
>>
>> If you mean FPU exceptions, maybe.
>>
>> As far as general interrupt handling, mechanism isn't too far off from
>> what SH-4 had used, and apparently also RISC-V's CLINT and MIPS work in
>> a similar way.
>>
>> Though, with differences as to how they divide up exceptions.
>>    In my case:
>>      Reset;
>>      General Fault;
>>      External Interrupt;
>>      TLB/MMU;
>>      Syscall.
> 
> 
> Integer Overflow

Not usually a thing. Pretty much everything seems to treat integer 
overflow as silently wrapping.


> Bad Instruction encoding--OpCode exists but not as this
>     instruction uses it. Random code generation can use
>     every instruction without privilege.

Hit or miss.

Will usually fault on invalid instructions.

There is logic in place to reject privileged instructions in user-mode, 
if the CPU is actually run in user-mode. Some of this is still TODO 
(currently, TestKern is still running everything in Supervisor Mode).


The alternative is to treat them as UB, so they may be one of:
   Trap;
   Do something else (like, if an instruction was added);
   Do something wonky / unintended.

In practice, this seems to be more how it works.



 > Bad address--address exists but you are not allowed to touch it>     
with LD or ST instruction or to attempt to execute it.

If the MMU is enabled, it should fault on bad memory accesses.

In physical addressing mode, it does not trap.


IIRC, there was a mechanism on the bus to deal with accesses to bad 
physical addresses (returning all zeroes). Otherwise, trying to access 
an invalid address would cause the CPU to deadlock.


One other option could be a TTL, say, where a request times out and 
"decays' into a response if it cycles the bus for long enough.


>>
>>> Proper IEEE 754-2018 handling of FMAC (compute all the  bits)
>>
>> Possibly true.
>> My FPU can more-or-less pass the 1985 spec, but not the 2018 spec.
> 
> As I understand it, you don't even get FMUL correctly rounded.
> To get it properly rounded you have to compute the full 53*53
> product.

AFAICT, this wasn't required for the 1985 spec...

Things like "optional trap on denormal" seems like it should be OK (this 
is what MIPS and friends did at the time).

For the most part, seems like the '85 spec was more "uses these formats 
and gets more or less the same values, good enough". A lot of the 
pedantic rounding stuff, etc, seemed to be more something for the 2008 spec.



The lack of single-rounded FMA shouldn't matter, since this wasn't added 
until later.

Support for Binary16 is a bonus feature (since 85 spec only gave Single 
/ Double / Extended), but Binary16 is useful...


>>
>>> Floating Point Transcendentals
>>
>> Not present in many/most ISA's I have looked at.
> 
> Its time has come.
> 

Then who has done it, besides x87 and similar?...

Not going to put much weight in something if:
The only real known example is the legacy x87 ISA;
Pretty much everyone else (including on x86-64) is using unrolled 
Taylor-series expansion and similar.



>>> HyperVisors/Secure Monitors
>>
>> Possible. I had considered doing it essentially with emulators, but
>> granted, this is not quite the same thing.
> 
> How can something of lesser privilege emulate something of greater
> privilege ??
> 

Top level OS (or hypervisor layer) runs an emulator, which runs any VMs 
holding guest OS instances.


Granted, running the main OS in an emulator wouldn't be great for 
performance. But, in most contexts, this isn't really a thing.

Like, pretty sure Windows and Linux still tend to run bare-metal on most 
systems, ... (or, if a VM layer exists, it is unclear what if-any 
purpose it would serve).


But, in any case, one doesn't need any special ISA level support to make 
things like QEMU and DOSBox work.

And, if a person wants to essentially use something like QEMU to run the 
whole OS, nothing really is stopping them.

Well, except maybe how slow that QEMU and DOSBox tend to be on something 
like a RasPi (on a 50MHz CPU, one would likely be hard-pressed to even 
run something like SimCity at acceptable speeds).


Not yet tried porting something like DOSBox to my stuff though...


But, a more clever emulator could likely leverage things like hardware 
address translation and maybe only JIT parts of the target system (vs, 
say, fully emulating the memory access and using JIT compilation or 
interpretation for "pretty much everything").

Say, for example, if the host system and guest OS are running the same 
ISA (vs, say, the guest OS running x86 or x86-64; on a host running a 
different ISA).


>>
>> Seems many of the extant RV implementations don't have this either.
> 
> Then not of Industrial quality !!
> 

They are releasing a lot of devboards.

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