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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Wed, 4 Sep 2024 18:54:23 -0700
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On 9/4/2024 5:59 PM, MitchAlsup1 wrote:
> On Wed, 4 Sep 2024 23:48:48 +0000, Chris M. Thomasson wrote:
> 
>> On 9/4/2024 2:27 PM, MitchAlsup1 wrote:
>>> On Mon, 2 Sep 2024 17:27:57 +0000, jseigh wrote:
>>>
>>>> I read that arm added the cas instruction because they didn't think
>>>> ldxr/stxr would scale well.  It wasn't clear to me as to why that
>>>> would be the case.  I would think the memory lock mechanism would
>>>> have really low overhead vs cas having to do an interlocked load
>>>> and store.  Unless maybe the memory lock size might be large
>>>> enough to cause false sharing issues.  Any ideas?
>>>
>>> A pipeline lock between the LD part of a CAS and the ST part of a
>>> CAS is essentially FREE. But the same is true for LL followed by
>>> a later SC.
>>
>> 100% sure on that? No way to break the reservation from an unrelated
>> aspect wrt LL/SC?
> 
> I have been building pipelines like that since 1983.
> 
> Now, it is completely possible to build a pipeline that gives
> one grief (lesser or greater) in doing these things--but it is
> definitely possible to build a grief free pipeline for LL- SC,
> and by extension CAS.

Well, the software must play along as well? Padded and aligned on 
certain boundaries helps things out. Big time.