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From: jseigh <jseigh_es00@xemaps.com>
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Thu, 5 Sep 2024 07:33:23 -0400
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On 9/4/2024 5:27 PM, MitchAlsup1 wrote:
> On Mon, 2 Sep 2024 17:27:57 +0000, jseigh wrote:
> 
>> I read that arm added the cas instruction because they didn't think
>> ldxr/stxr would scale well.  It wasn't clear to me as to why that
>> would be the case.  I would think the memory lock mechanism would
>> have really low overhead vs cas having to do an interlocked load
>> and store.  Unless maybe the memory lock size might be large
>> enough to cause false sharing issues.  Any ideas?
> 
> A pipeline lock between the LD part of a CAS and the ST part of a
> CAS is essentially FREE. But the same is true for LL followed by
> a later SC.
> 
> Older machines with looser than sequential consistency memory models
> and running OoO have a myriad of problems with LL - SC. This is
> why My 66000 architecture switches from causal consistency to
> sequential consistency when it encounters <effectively> LL and
> switches bac after seeing SC.
> 
> No Fences necessary with causal consistency.
> 

I'm not sure I entirely follow.  I was thinking of the effects on
cache.  In theory the SC could fail without having get the current
cache line exclusive or at all.  CAS has to get it exclusive before
it can definitively fail.

Whenever they get around to making arm desktops without the OS tax
so I can install linux I can compare the 2.

Joe Seigh