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From: David Brown <david.brown@hesbynett.no>
Newsgroups: comp.lang.c
Subject: Re: Top 10 most common hard skills listed on resumes...
Date: Tue, 10 Sep 2024 11:20:55 +0200
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On 10/09/2024 01:58, Waldek Hebisch wrote:
> David Brown <david.brown@hesbynett.no> wrote:
>> On 09/09/2024 16:36, Waldek Hebisch wrote:
>>> David Brown <david.brown@hesbynett.no> wrote:
>>>> On 08/09/2024 23:34, Waldek Hebisch wrote:
>>>>> David Brown <david.brown@hesbynett.no> wrote:
>>>>>>
>>>>>> And while microcontrollers sometimes have a limited form of branch
>>>>>> prediction (such as prefetching the target from cache), the more
>>>>>> numerous and smaller devices don't even have instruction caches.
>>>>>> Certainly none of them have register renaming or speculative execution.
>>>>>
>>>>> IIUC STM4 series has cache, and some of them are not so big.  There
>>>>> are now several chinese variants of STM32F103 and some of them have
>>>>> caches (some very small like 32 words, IIRC one has 8 words and it
>>>>> is hard to decide if this very small cache or big prefetch buffer).
>>>>
>>>> There are different kinds of cache here.  Some of the Cortex-M cores
>>>> have optional caches (i.e., the microcontroller manufacturer can choose
>>>> to have them or not).
>>>>
>>>> <https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization>
>>>
>>> I do not see relevent information at that link.
>>
>> There is a table of the Cortex-M cores, with the sizes of the optional
>> caches.
>>
>>>    
>>>> Flash memory, flash controller peripherals, external memory interfaces
>>>> (including things like QSPI) are all specific to the manufacturer,
>>>> rather than part of the Cortex M cores from ARM.  Manufacturers can do
>>>> whatever they want there.
>>>
>>> AFAIK typical Cortex-M design has core connected to "bus matrix".
>>> It is up to chip vendor to decide what else is connected to bus matrix.
>>
>> Yes.
>>
>> However, there are other things connected before these crossbar
>> switches, such as tightly-coupled memory (if any).
> 
> TCM is _not_ a cache.
> 

Correct.  (I did not suggest or imply that it was.)

>>   And the cpu caches
>> (if any) are on the cpu side of the switches.
> 
> Caches are attached were system designer thinks they are useful
> (and possible).  Word "cache" has well-estabished meaning and
> ARM (or you) has no right to redefine it.
> 

I am using it in the manner ARM uses it when talking about ARM 
processors and microcontroller cores.  I think that is the most relevant 
way to use the term here.  The term "cache" has many meanings in many 
contexts - there is no single precise "well-established" or "official" 
meaning.  Context is everything.  That is why I have been using the term 
"cpu cache" for the cache tied tightly to the cpu itself, which comes as 
part of the core that ARM designs and delivers, along with parts such as 
the NVIC.  And I have tried to use terms such as "buffer" or "flash 
controller cache" for the memory buffers often provided as part of flash 
controllers and memory interfaces on microcontrollers, because those are 
terms used by the microcontroller manufacturers.

>>   Manufacturers also have a
>> certain amount of freedom of the TCMs and caches, depending on which
>> core they are using and which licenses they have.
>>
>> There is a convenient diagram here:
>>
>> <https://www.electronicdesign.com/technologies/embedded/digital-ics/processors/microcontrollers/article/21800516/cortex-m7-contains-configurable-tightly-coupled-memory>
>>
>>> For me it does not matter if it is ARM design or vendor specific.
>>> Normal internal RAM is accessed via bus matrix, and in MCU-s that
>>> I know about is fast enough so that cache is not needed.  So caches
>>> come into play only for flash (and possibly external memory, but
>>> design with external memory probably will be rather large).
>>>
>>
>> Typically you see data caches on faster Cortex-M4 microcontrollers with
>> external DRAM, and it is also standard on Cortex-M7 devices.  For the
>> faster chips, internal SRAM on the AXI bus is not fast enough.  For
>> example, the NXP i.mx RT106x family typically run at 528 MHz core clock,
>> but the AXI bus and cross-switch are at 133 MHz (a quarter of the
>> speed).  The tightly-coupled memories and the caches run at full core speed.
> 
> OK, if you run core at faster clock than the bus matrix, then cache
> attached on core side make a lot of sense.  And since cache has to
> compensate for lower bus speed it must be resonably large.  

Yes.

> But
> if you look at devices where bus matrix runs at the same clock
> as the core, then it makes sense to put cache on the other side.

No.

You put caches as close as possible to the prime user of the cache.  If 
the prime user is the cpu and you want to cache data from flash, 
external memory, and other sources, you put the cache tight up against 
the cpu - then you can have dedicated, wide, fast buses to the cpu.

But it can also make sense to put small buffers as part of memory 
interface controllers.  These are not organized like data or instruction 
caches, but are specific for the type of memory and the characteristics 
of it.  How this is done depends on details of the interface, details of 
the internal buses, and how the manufacturer wants to implement it.  For 
example, on one microcontroller I am using there are queues to let it 
accept multiple flash read/write commands from the AHB bus and the IPS 
bus, but read-ahead is controlled by the burst length of read requests 
from the cross-switch (which in turn will come from cache line fill 
requests from the cpu caches).  On a different microcontroller, the 
read-ahead logic is in the flash controller itself as that chip has a 
simpler internal bus where all read requests will be for 32 bits (it has 
no cpu caches).  An external DRAM controller, on the other hand, will 
have queues and buffers optimised for multiple smaller transactions and 
be able to hold writes in queues that get lower priority than read requests.

These sorts of queues and buffers are not generally referred to as 
"caches", because they are specialised queues and buffers.  Sometimes 
you might have something that is in effect perhaps a two-way 
single-entry 16 byte wide read-only cache, but using the term "cache" 
here is often confusing.  At best it is a "flash controller cache", and 
very distinct from a "cpu cache".

> 
>>> It seems that vendor do not like to say that they use cache, instead
>>> that use misleading terms like "flash accelerator".
>>
>> That all depends on the vendor, and on how the flash interface
>> controller.  Vendors do like to use terms that sound good, of course!
>>
>>>
>>>> So a "cache" of 32 words is going to be part of the flash interface, not
>>>> a cpu cache
>>>
>>> Well, caches never were part of CPU proper, they were part of
>>> memory interface.  They could act for whole memory or only for part
>>> that need it (like flash).  So I do not understand what "not a cpu
>>> cache" is supposed to mean.  More relevant is if such thing act
>>> as a cache, 32 word things almost surely will act as a cache,
>>> 8 word thing may be a simple FIFO buffer (or may act smarter
>>> showing behaviour typical of caches).
>>>
>>
>> Look at the diagram in the link I gave above, as an example.  CPU caches
>> are part of the block provided by ARM and are tightly connected to the
>> processor.  Control of the caches (such as for enabling them) is done by
>> hardware registers provided by ARM, alongside the NVIC interrupt
>> controller, SysTick, MPU, and other units (depending on the exact
>> Cortex-M model).
>>
>> This is completely different from the small buffers that are often
>> included in flash controllers or external memory interfaces as
>> read-ahead buffers or write queues (for RAM), which are as external the
>> processor core as SPI, UART, PWM, ADC, and other common blocks provided
>> by the microcontroller manufacturer.
> 
> The disscussion started about possible interaction of caches
> and virtual function dispatch.

OK - I admit to having lost track of the earlier discussion, so that is 
helpful.

>  This interaction does not depend
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