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From: jseigh <jseigh_es00@xemaps.com>
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Tue, 10 Sep 2024 17:34:28 -0400
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On 9/10/24 14:46, Chris M. Thomasson wrote:
> On 9/10/2024 7:40 AM, jseigh wrote:
>>
>>
>> One of the things I have in my implementation is that an enqueue
>> operation can detect if wrap occurred if it got a interrupted by
>> a time slice end and log how far behind it got.  I'm seeing about
>> 200,000 enqueue operations in those cases.  That would have been
>> a huge performance hit if my queue wasn't lock-free.
> 
> Is your queue similar to the M&S Queue?
> 
> https://people.csail.mit.edu/xchen/parallel-computing/queue.pdf
> 

Yes.